a8a9f3fef1
The STM SPEAr platform can only access the i2c controller register via 16bit read/write functions. This patch adds support to automatically detect this 16bit access mode. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
108 lines
3.7 KiB
C
108 lines
3.7 KiB
C
/*
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* Synopsys DesignWare I2C adapter driver (master only).
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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*/
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#define DW_IC_CON_MASTER 0x1
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#define DW_IC_CON_SPEED_STD 0x2
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#define DW_IC_CON_SPEED_FAST 0x4
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#define DW_IC_CON_10BITADDR_MASTER 0x10
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#define DW_IC_CON_RESTART_EN 0x20
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#define DW_IC_CON_SLAVE_DISABLE 0x40
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/**
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* struct dw_i2c_dev - private i2c-designware data
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* @dev: driver model device node
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* @base: IO registers pointer
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* @cmd_complete: tx completion indicator
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* @lock: protect this struct and IO registers
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* @clk: input reference clock
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* @cmd_err: run time hadware error code
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* @msgs: points to an array of messages currently being transfered
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* @msgs_num: the number of elements in msgs
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* @msg_write_idx: the element index of the current tx message in the msgs
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* array
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* @tx_buf_len: the length of the current tx buffer
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* @tx_buf: the current tx buffer
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* @msg_read_idx: the element index of the current rx message in the msgs
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* array
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* @rx_buf_len: the length of the current rx buffer
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* @rx_buf: the current rx buffer
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* @msg_err: error status of the current transfer
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* @status: i2c master status, one of STATUS_*
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* @abort_source: copy of the TX_ABRT_SOURCE register
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* @irq: interrupt number for the i2c master
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* @adapter: i2c subsystem adapter node
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* @tx_fifo_depth: depth of the hardware tx fifo
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* @rx_fifo_depth: depth of the hardware rx fifo
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*/
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struct dw_i2c_dev {
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struct device *dev;
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void __iomem *base;
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struct completion cmd_complete;
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struct mutex lock;
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struct clk *clk;
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u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
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struct dw_pci_controller *controller;
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int cmd_err;
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struct i2c_msg *msgs;
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int msgs_num;
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int msg_write_idx;
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u32 tx_buf_len;
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u8 *tx_buf;
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int msg_read_idx;
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u32 rx_buf_len;
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u8 *rx_buf;
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int msg_err;
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unsigned int status;
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u32 abort_source;
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int irq;
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u32 accessor_flags;
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struct i2c_adapter adapter;
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u32 functionality;
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u32 master_cfg;
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unsigned int tx_fifo_depth;
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unsigned int rx_fifo_depth;
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};
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#define ACCESS_SWAP 0x00000001
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#define ACCESS_16BIT 0x00000002
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extern u32 dw_readl(struct dw_i2c_dev *dev, int offset);
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extern void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
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extern int i2c_dw_init(struct dw_i2c_dev *dev);
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extern int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
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int num);
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extern u32 i2c_dw_func(struct i2c_adapter *adap);
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extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id);
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extern void i2c_dw_enable(struct dw_i2c_dev *dev);
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extern u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev);
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extern void i2c_dw_disable(struct dw_i2c_dev *dev);
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extern void i2c_dw_clear_int(struct dw_i2c_dev *dev);
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extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
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extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
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