Oskar Schirmer a81cbd2da4 xtensa: enforce slab alignment to maximum register width ... XCHAL_DATA_WIDTH is the maximum register width, slab caches should be aligned to this. Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4 (wordsize) for now. But the S6000 variant will raise this to 16. Signed-off-by: Oskar Schirmer <os@emlix.com> Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>		2009-04-02 23:41:16 -07:00
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boot	xtensa: move headers files to arch/xtensa/include	2008-11-06 10:25:09 -08:00
configs	[PATCH] xtensa: remove extra header files	2006-12-10 09:55:39 -08:00
include/asm	xtensa: enforce slab alignment to maximum register width	2009-04-02 23:41:16 -07:00
kernel	xtensa: use correct stack pointer for stack traces	2009-04-02 23:38:57 -07:00
lib	xtensa: move headers files to arch/xtensa/include	2008-11-06 10:25:09 -08:00
mm	xtensa: cope with ram beginning at higher addresses	2009-04-02 23:41:08 -07:00
platforms	proc tty: switch xtensa iss console to ->proc_fops	2009-04-01 08:59:10 -07:00
variants	xtensa: move headers files to arch/xtensa/include	2008-11-06 10:25:09 -08:00
Kconfig	xtensa: beat Kconfig into shape	2009-04-02 23:38:35 -07:00
Kconfig.debug	[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 1	2005-06-24 00:05:21 -07:00
Makefile	xtensa: move headers files to arch/xtensa/include	2008-11-06 10:25:09 -08:00