deae6e3a42
[ Upstream commit 8614afd689df59d9ce019439389be20bd788a897 ]
When putting the port in reset, driver must wait for the soft reset
acknowledgment bit instead of the soft reset bit.
Fixes:
|
||
---|---|---|
.. | ||
altera-cvp.c | ||
altera-fpga2sdram.c | ||
altera-freeze-bridge.c | ||
altera-hps2fpga.c | ||
altera-pr-ip-core-plat.c | ||
altera-pr-ip-core.c | ||
altera-ps-spi.c | ||
dfl-afu-dma-region.c | ||
dfl-afu-main.c | ||
dfl-afu-region.c | ||
dfl-afu.h | ||
dfl-fme-br.c | ||
dfl-fme-main.c | ||
dfl-fme-mgr.c | ||
dfl-fme-pr.c | ||
dfl-fme-pr.h | ||
dfl-fme-region.c | ||
dfl-fme.h | ||
dfl-pci.c | ||
dfl.c | ||
dfl.h | ||
fpga-bridge.c | ||
fpga-mgr.c | ||
fpga-region.c | ||
ice40-spi.c | ||
Kconfig | ||
machxo2-spi.c | ||
Makefile | ||
of-fpga-region.c | ||
socfpga-a10.c | ||
socfpga.c | ||
ts73xx-fpga.c | ||
xilinx-pr-decoupler.c | ||
xilinx-spi.c | ||
zynq-fpga.c |