..
cache-disabled.c
cache-flush-by-reg.S
MN10300: AM34: Add cacheflushing by using the AM34 purge registers
2010-10-27 17:28:45 +01:00
cache-flush-by-tag.S
MN10300: SMP: Differentiate local cache flushing
2010-10-27 17:28:45 +01:00
cache-flush-icache.c
MN10300: Cache: Implement SMP global cache flushing
2010-10-27 17:28:47 +01:00
cache-inv-by-reg.S
MN10300: AM34: Add cacheflushing by using the AM34 purge registers
2010-10-27 17:28:45 +01:00
cache-inv-by-tag.S
MN10300: SMP: Differentiate local cache flushing
2010-10-27 17:28:45 +01:00
cache-inv-icache.c
MN10300: The SMP_ICACHE_INV_FLUSH_RANGE IPI command does not exist
2011-03-14 14:45:29 +00:00
cache-smp-flush.c
MN10300: Cache: Implement SMP global cache flushing
2010-10-27 17:28:47 +01:00
cache-smp-inv.c
MN10300: Cache: Implement SMP global cache flushing
2010-10-27 17:28:47 +01:00
cache-smp.c
MN10300: Cache: Implement SMP global cache flushing
2010-10-27 17:28:47 +01:00
cache-smp.h
MN10300: Cache: Implement SMP global cache flushing
2010-10-27 17:28:47 +01:00
cache.c
MN10300: Cache: Implement SMP global cache flushing
2010-10-27 17:28:47 +01:00
dma-alloc.c
extable.c
fault.c
MN10300: And Panasonic AM34 subarch and implement SMP
2010-10-27 17:28:55 +01:00
init.c
MN10300: Map userspace atomic op regs as a vmalloc page
2010-10-27 17:28:56 +01:00
Kconfig.cache
MN10300: Cache: Implement SMP global cache flushing
2010-10-27 17:28:47 +01:00
Makefile
MN10300: SMP TLB flushing
2010-10-27 17:28:51 +01:00
misalignment.c
mmu-context.c
MN10300: Make the use of PIDR to mark TLB entries controllable
2010-10-27 17:28:49 +01:00
pgtable.c
MN10300: Rename __flush_tlb*() to local_flush_tlb*()
2010-10-27 17:28:49 +01:00
tlb-mn10300.S
MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control
2010-10-27 17:28:50 +01:00
tlb-smp.c
MN10300: SMP TLB flushing
2010-10-27 17:28:51 +01:00