a5decf700b
MSI IRQ numbers are allocated dynamically, so there is no reason to have all these static definitions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
182 lines
5.4 KiB
C
182 lines
5.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008 Cavium Networks
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*/
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#ifndef __OCTEON_IRQ_H__
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#define __OCTEON_IRQ_H__
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#define NR_IRQS OCTEON_IRQ_LAST
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#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
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/* 0 - 7 represent the i8259 master */
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#define OCTEON_IRQ_I8259M0 0
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#define OCTEON_IRQ_I8259M1 1
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#define OCTEON_IRQ_I8259M2 2
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#define OCTEON_IRQ_I8259M3 3
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#define OCTEON_IRQ_I8259M4 4
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#define OCTEON_IRQ_I8259M5 5
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#define OCTEON_IRQ_I8259M6 6
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#define OCTEON_IRQ_I8259M7 7
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/* 8 - 15 represent the i8259 slave */
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#define OCTEON_IRQ_I8259S0 8
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#define OCTEON_IRQ_I8259S1 9
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#define OCTEON_IRQ_I8259S2 10
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#define OCTEON_IRQ_I8259S3 11
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#define OCTEON_IRQ_I8259S4 12
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#define OCTEON_IRQ_I8259S5 13
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#define OCTEON_IRQ_I8259S6 14
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#define OCTEON_IRQ_I8259S7 15
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/* 16 - 23 represent the 8 MIPS standard interrupt sources */
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#define OCTEON_IRQ_SW0 16
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#define OCTEON_IRQ_SW1 17
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#define OCTEON_IRQ_CIU0 18
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#define OCTEON_IRQ_CIU1 19
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#define OCTEON_IRQ_CIU4 20
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#define OCTEON_IRQ_5 21
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#define OCTEON_IRQ_PERF 22
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#define OCTEON_IRQ_TIMER 23
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/* 24 - 87 represent the sources in CIU_INTX_EN0 */
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#define OCTEON_IRQ_WORKQ0 24
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#define OCTEON_IRQ_WORKQ1 25
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#define OCTEON_IRQ_WORKQ2 26
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#define OCTEON_IRQ_WORKQ3 27
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#define OCTEON_IRQ_WORKQ4 28
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#define OCTEON_IRQ_WORKQ5 29
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#define OCTEON_IRQ_WORKQ6 30
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#define OCTEON_IRQ_WORKQ7 31
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#define OCTEON_IRQ_WORKQ8 32
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#define OCTEON_IRQ_WORKQ9 33
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#define OCTEON_IRQ_WORKQ10 34
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#define OCTEON_IRQ_WORKQ11 35
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#define OCTEON_IRQ_WORKQ12 36
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#define OCTEON_IRQ_WORKQ13 37
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#define OCTEON_IRQ_WORKQ14 38
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#define OCTEON_IRQ_WORKQ15 39
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#define OCTEON_IRQ_GPIO0 40
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#define OCTEON_IRQ_GPIO1 41
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#define OCTEON_IRQ_GPIO2 42
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#define OCTEON_IRQ_GPIO3 43
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#define OCTEON_IRQ_GPIO4 44
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#define OCTEON_IRQ_GPIO5 45
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#define OCTEON_IRQ_GPIO6 46
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#define OCTEON_IRQ_GPIO7 47
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#define OCTEON_IRQ_GPIO8 48
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#define OCTEON_IRQ_GPIO9 49
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#define OCTEON_IRQ_GPIO10 50
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#define OCTEON_IRQ_GPIO11 51
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#define OCTEON_IRQ_GPIO12 52
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#define OCTEON_IRQ_GPIO13 53
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#define OCTEON_IRQ_GPIO14 54
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#define OCTEON_IRQ_GPIO15 55
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#define OCTEON_IRQ_MBOX0 56
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#define OCTEON_IRQ_MBOX1 57
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#define OCTEON_IRQ_UART0 58
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#define OCTEON_IRQ_UART1 59
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#define OCTEON_IRQ_PCI_INT0 60
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#define OCTEON_IRQ_PCI_INT1 61
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#define OCTEON_IRQ_PCI_INT2 62
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#define OCTEON_IRQ_PCI_INT3 63
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#define OCTEON_IRQ_PCI_MSI0 64
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#define OCTEON_IRQ_PCI_MSI1 65
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#define OCTEON_IRQ_PCI_MSI2 66
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#define OCTEON_IRQ_PCI_MSI3 67
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#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */
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#define OCTEON_IRQ_TWSI 69
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#define OCTEON_IRQ_RML 70
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#define OCTEON_IRQ_TRACE 71
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#define OCTEON_IRQ_GMX_DRP0 72
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#define OCTEON_IRQ_GMX_DRP1 73
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#define OCTEON_IRQ_IPD_DRP 74
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#define OCTEON_IRQ_KEY_ZERO 75
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#define OCTEON_IRQ_TIMER0 76
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#define OCTEON_IRQ_TIMER1 77
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#define OCTEON_IRQ_TIMER2 78
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#define OCTEON_IRQ_TIMER3 79
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#define OCTEON_IRQ_USB0 80
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#define OCTEON_IRQ_PCM 81
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#define OCTEON_IRQ_MPI 82
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#define OCTEON_IRQ_TWSI2 83
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#define OCTEON_IRQ_POWIQ 84
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#define OCTEON_IRQ_IPDPPTHR 85
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#define OCTEON_IRQ_MII0 86
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#define OCTEON_IRQ_BOOTDMA 87
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/* 88 - 151 represent the sources in CIU_INTX_EN1 */
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#define OCTEON_IRQ_WDOG0 88
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#define OCTEON_IRQ_WDOG1 89
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#define OCTEON_IRQ_WDOG2 90
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#define OCTEON_IRQ_WDOG3 91
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#define OCTEON_IRQ_WDOG4 92
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#define OCTEON_IRQ_WDOG5 93
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#define OCTEON_IRQ_WDOG6 94
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#define OCTEON_IRQ_WDOG7 95
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#define OCTEON_IRQ_WDOG8 96
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#define OCTEON_IRQ_WDOG9 97
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#define OCTEON_IRQ_WDOG10 98
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#define OCTEON_IRQ_WDOG11 99
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#define OCTEON_IRQ_WDOG12 100
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#define OCTEON_IRQ_WDOG13 101
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#define OCTEON_IRQ_WDOG14 102
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#define OCTEON_IRQ_WDOG15 103
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#define OCTEON_IRQ_UART2 104
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#define OCTEON_IRQ_USB1 105
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#define OCTEON_IRQ_MII1 106
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#define OCTEON_IRQ_RESERVED107 107
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#define OCTEON_IRQ_RESERVED108 108
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#define OCTEON_IRQ_RESERVED109 109
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#define OCTEON_IRQ_RESERVED110 110
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#define OCTEON_IRQ_RESERVED111 111
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#define OCTEON_IRQ_RESERVED112 112
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#define OCTEON_IRQ_RESERVED113 113
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#define OCTEON_IRQ_RESERVED114 114
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#define OCTEON_IRQ_RESERVED115 115
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#define OCTEON_IRQ_RESERVED116 116
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#define OCTEON_IRQ_RESERVED117 117
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#define OCTEON_IRQ_RESERVED118 118
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#define OCTEON_IRQ_RESERVED119 119
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#define OCTEON_IRQ_RESERVED120 120
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#define OCTEON_IRQ_RESERVED121 121
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#define OCTEON_IRQ_RESERVED122 122
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#define OCTEON_IRQ_RESERVED123 123
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#define OCTEON_IRQ_RESERVED124 124
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#define OCTEON_IRQ_RESERVED125 125
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#define OCTEON_IRQ_RESERVED126 126
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#define OCTEON_IRQ_RESERVED127 127
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#define OCTEON_IRQ_RESERVED128 128
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#define OCTEON_IRQ_RESERVED129 129
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#define OCTEON_IRQ_RESERVED130 130
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#define OCTEON_IRQ_RESERVED131 131
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#define OCTEON_IRQ_RESERVED132 132
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#define OCTEON_IRQ_RESERVED133 133
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#define OCTEON_IRQ_RESERVED134 134
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#define OCTEON_IRQ_RESERVED135 135
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#define OCTEON_IRQ_RESERVED136 136
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#define OCTEON_IRQ_RESERVED137 137
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#define OCTEON_IRQ_RESERVED138 138
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#define OCTEON_IRQ_RESERVED139 139
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#define OCTEON_IRQ_RESERVED140 140
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#define OCTEON_IRQ_RESERVED141 141
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#define OCTEON_IRQ_RESERVED142 142
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#define OCTEON_IRQ_RESERVED143 143
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#define OCTEON_IRQ_RESERVED144 144
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#define OCTEON_IRQ_RESERVED145 145
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#define OCTEON_IRQ_RESERVED146 146
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#define OCTEON_IRQ_RESERVED147 147
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#define OCTEON_IRQ_RESERVED148 148
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#define OCTEON_IRQ_RESERVED149 149
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#define OCTEON_IRQ_RESERVED150 150
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#define OCTEON_IRQ_RESERVED151 151
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#ifdef CONFIG_PCI_MSI
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/* 152 - 215 represent the MSI interrupts 0-63 */
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#define OCTEON_IRQ_MSI_BIT0 152
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 63)
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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#else
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#define OCTEON_IRQ_LAST 152
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#endif
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#endif
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