809f36c6f4
Add basic support for the Au1300 variant(s): - New GPIO/Interrupt controller - DBDMA ids - USB setup - MMC support - enable various PSC drivers - detection code. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
86 lines
2.5 KiB
C
86 lines
2.5 KiB
C
/*
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* Alchemy GPIO support.
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*
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* With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within
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* the same kernel image.
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* With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the
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* appropriate CPU type (AU1000 currently).
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*/
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#ifndef _ALCHEMY_GPIO_H_
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#define _ALCHEMY_GPIO_H_
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/gpio-au1000.h>
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#include <asm/mach-au1x00/gpio-au1300.h>
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/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
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* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
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* register enables use of GPIOs as wake source.
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*/
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static inline void alchemy_gpio1_input_enable(void)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
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__raw_writel(0, base + 0x110); /* the write op is key */
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wmb();
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}
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/* Linux gpio framework integration.
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*
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* 4 use cases of Alchemy GPIOS:
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*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
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* Board must register gpiochips.
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*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
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* A gpiochip for the 75 GPIOs is registered.
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*
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*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
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* the boards' gpio.h must provide the linux gpio wrapper functions,
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*
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*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
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* inlinable gpio functions are provided which enable access to the
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* Au1300 gpios only by using the numbers straight out of the data-
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* sheets.
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* Cases 1 and 3 are intended for boards which want to provide their own
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* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
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* which are in part provided by spare Au1300 GPIO pins and in part by
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* an external FPGA but you still want them to be accssible in linux
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* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
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* as required).
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*/
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#ifdef CONFIG_GPIOLIB
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/* wraps the cpu-dependent irq_to_gpio functions */
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/* FIXME: gpiolib needs an irq_to_gpio hook */
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static inline int __au_irq_to_gpio(unsigned int irq)
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{
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
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return alchemy_irq_to_gpio(irq);
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case ALCHEMY_CPU_AU1300:
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return au1300_irq_to_gpio(irq);
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}
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return -EINVAL;
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}
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/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
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#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
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/* get everything through gpiolib */
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#define gpio_to_irq __gpio_to_irq
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#define gpio_get_value __gpio_get_value
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#define gpio_set_value __gpio_set_value
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#define gpio_cansleep __gpio_cansleep
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#define irq_to_gpio __au_irq_to_gpio
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#include <asm-generic/gpio.h>
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#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
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#endif /* CONFIG_GPIOLIB */
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#endif /* _ALCHEMY_GPIO_H_ */
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