279 lines
6.3 KiB
Text
279 lines
6.3 KiB
Text
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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};
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tzic: tz-interrupt-controller@e0000000 {
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compatible = "fsl,imx51-tzic", "fsl,tzic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xe0000000 0x4000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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clock-frequency = <22579200>;
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};
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ckih2 {
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compatible = "fsl,imx-ckih2", "fixed-clock";
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&tzic>;
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ranges;
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aips@70000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x70000000 0x10000000>;
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ranges;
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spba@70000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x70000000 0x40000>;
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ranges;
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esdhc@70004000 { /* ESDHC1 */
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compatible = "fsl,imx51-esdhc";
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reg = <0x70004000 0x4000>;
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interrupts = <1>;
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status = "disabled";
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};
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esdhc@70008000 { /* ESDHC2 */
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compatible = "fsl,imx51-esdhc";
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reg = <0x70008000 0x4000>;
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interrupts = <2>;
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status = "disabled";
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};
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uart3: serial@7000c000 {
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x7000c000 0x4000>;
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interrupts = <33>;
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status = "disabled";
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};
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ecspi@70010000 { /* ECSPI1 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-ecspi";
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reg = <0x70010000 0x4000>;
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interrupts = <36>;
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status = "disabled";
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};
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ssi2: ssi@70014000 {
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compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
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reg = <0x70014000 0x4000>;
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interrupts = <30>;
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fsl,fifo-depth = <15>;
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fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
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status = "disabled";
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};
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esdhc@70020000 { /* ESDHC3 */
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compatible = "fsl,imx51-esdhc";
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reg = <0x70020000 0x4000>;
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interrupts = <3>;
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status = "disabled";
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};
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esdhc@70024000 { /* ESDHC4 */
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compatible = "fsl,imx51-esdhc";
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reg = <0x70024000 0x4000>;
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interrupts = <4>;
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status = "disabled";
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};
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};
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gpio1: gpio@73f84000 {
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f84000 0x4000>;
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interrupts = <50 51>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio2: gpio@73f88000 {
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f88000 0x4000>;
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interrupts = <52 53>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio3: gpio@73f8c000 {
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f8c000 0x4000>;
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interrupts = <54 55>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio4: gpio@73f90000 {
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f90000 0x4000>;
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interrupts = <56 57>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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wdog@73f98000 { /* WDOG1 */
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compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
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reg = <0x73f98000 0x4000>;
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interrupts = <58>;
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status = "disabled";
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};
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wdog@73f9c000 { /* WDOG2 */
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compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
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reg = <0x73f9c000 0x4000>;
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interrupts = <59>;
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status = "disabled";
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};
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uart1: serial@73fbc000 {
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x73fbc000 0x4000>;
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interrupts = <31>;
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status = "disabled";
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};
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uart2: serial@73fc0000 {
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x73fc0000 0x4000>;
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interrupts = <32>;
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status = "disabled";
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};
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};
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aips@80000000 { /* AIPS2 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x80000000 0x10000000>;
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ranges;
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ecspi@83fac000 { /* ECSPI2 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-ecspi";
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reg = <0x83fac000 0x4000>;
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interrupts = <37>;
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status = "disabled";
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};
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sdma@83fb0000 {
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compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
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reg = <0x83fb0000 0x4000>;
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interrupts = <6>;
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};
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cspi@83fc0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
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reg = <0x83fc0000 0x4000>;
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interrupts = <38>;
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status = "disabled";
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};
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i2c@83fc4000 { /* I2C2 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
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reg = <0x83fc4000 0x4000>;
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interrupts = <63>;
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status = "disabled";
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};
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i2c@83fc8000 { /* I2C1 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
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reg = <0x83fc8000 0x4000>;
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interrupts = <62>;
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status = "disabled";
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};
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ssi1: ssi@83fcc000 {
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compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
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reg = <0x83fcc000 0x4000>;
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interrupts = <29>;
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fsl,fifo-depth = <15>;
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fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
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status = "disabled";
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};
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audmux@83fd0000 {
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compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
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reg = <0x83fd0000 0x4000>;
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status = "disabled";
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};
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ssi3: ssi@83fe8000 {
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compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
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reg = <0x83fe8000 0x4000>;
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interrupts = <96>;
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fsl,fifo-depth = <15>;
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fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
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status = "disabled";
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};
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ethernet@83fec000 {
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compatible = "fsl,imx51-fec", "fsl,imx27-fec";
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reg = <0x83fec000 0x4000>;
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interrupts = <87>;
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status = "disabled";
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};
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};
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};
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};
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