fb8fcb8913
The patch adds base support for new TI SOC DM365, which s similar to the dm355. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
248 lines
4.1 KiB
C
248 lines
4.1 KiB
C
/*
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* Table of the DAVINCI register configurations for the PINMUX combinations
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*
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* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
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*
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* Based on linux/include/asm-arm/arch-omap/mux.h:
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* Copyright (C) 2003 - 2005 Nokia Corporation
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*
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* Written by Tony Lindgren
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Copyright (C) 2008 Texas Instruments.
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*/
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#ifndef __INC_MACH_MUX_H
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#define __INC_MACH_MUX_H
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struct mux_config {
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const char *name;
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const char *mux_reg_name;
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const unsigned char mux_reg;
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const unsigned char mask_offset;
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const unsigned char mask;
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const unsigned char mode;
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bool debug;
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};
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enum davinci_dm644x_index {
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/* ATA and HDDIR functions */
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DM644X_HDIREN,
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DM644X_ATAEN,
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DM644X_ATAEN_DISABLE,
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/* HPI functions */
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DM644X_HPIEN_DISABLE,
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/* AEAW functions */
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DM644X_AEAW,
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/* Memory Stick */
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DM644X_MSTK,
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/* I2C */
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DM644X_I2C,
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/* ASP function */
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DM644X_MCBSP,
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/* UART1 */
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DM644X_UART1,
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/* UART2 */
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DM644X_UART2,
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/* PWM0 */
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DM644X_PWM0,
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/* PWM1 */
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DM644X_PWM1,
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/* PWM2 */
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DM644X_PWM2,
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/* VLYNQ function */
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DM644X_VLYNQEN,
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DM644X_VLSCREN,
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DM644X_VLYNQWD,
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/* EMAC and MDIO function */
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DM644X_EMACEN,
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/* GPIO3V[0:16] pins */
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DM644X_GPIO3V,
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/* GPIO pins */
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DM644X_GPIO0,
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DM644X_GPIO3,
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DM644X_GPIO43_44,
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DM644X_GPIO46_47,
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/* VPBE */
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DM644X_RGB666,
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/* LCD */
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DM644X_LOEEN,
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DM644X_LFLDEN,
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};
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enum davinci_dm646x_index {
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/* ATA function */
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DM646X_ATAEN,
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/* AUDIO Clock */
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DM646X_AUDCK1,
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DM646X_AUDCK0,
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/* CRGEN Control */
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DM646X_CRGMUX,
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/* VPIF Control */
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DM646X_STSOMUX_DISABLE,
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DM646X_STSIMUX_DISABLE,
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DM646X_PTSOMUX_DISABLE,
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DM646X_PTSIMUX_DISABLE,
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/* TSIF Control */
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DM646X_STSOMUX,
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DM646X_STSIMUX,
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DM646X_PTSOMUX_PARALLEL,
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DM646X_PTSIMUX_PARALLEL,
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DM646X_PTSOMUX_SERIAL,
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DM646X_PTSIMUX_SERIAL,
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};
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enum davinci_dm355_index {
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/* MMC/SD 0 */
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DM355_MMCSD0,
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/* MMC/SD 1 */
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DM355_SD1_CLK,
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DM355_SD1_CMD,
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DM355_SD1_DATA3,
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DM355_SD1_DATA2,
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DM355_SD1_DATA1,
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DM355_SD1_DATA0,
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/* I2C */
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DM355_I2C_SDA,
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DM355_I2C_SCL,
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/* ASP0 function */
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DM355_MCBSP0_BDX,
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DM355_MCBSP0_X,
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DM355_MCBSP0_BFSX,
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DM355_MCBSP0_BDR,
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DM355_MCBSP0_R,
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DM355_MCBSP0_BFSR,
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/* SPI0 */
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DM355_SPI0_SDI,
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DM355_SPI0_SDENA0,
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DM355_SPI0_SDENA1,
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/* IRQ muxing */
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DM355_INT_EDMA_CC,
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DM355_INT_EDMA_TC0_ERR,
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DM355_INT_EDMA_TC1_ERR,
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/* EDMA event muxing */
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DM355_EVT8_ASP1_TX,
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DM355_EVT9_ASP1_RX,
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DM355_EVT26_MMC0_RX,
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};
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enum davinci_dm365_index {
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/* MMC/SD 0 */
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DM365_MMCSD0,
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/* MMC/SD 1 */
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DM365_SD1_CLK,
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DM365_SD1_CMD,
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DM365_SD1_DATA3,
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DM365_SD1_DATA2,
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DM365_SD1_DATA1,
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DM365_SD1_DATA0,
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/* I2C */
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DM365_I2C_SDA,
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DM365_I2C_SCL,
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/* AEMIF */
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DM365_AEMIF_AR,
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DM365_AEMIF_A3,
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DM365_AEMIF_A7,
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DM365_AEMIF_D15_8,
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DM365_AEMIF_CE0,
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/* ASP0 function */
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DM365_MCBSP0_BDX,
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DM365_MCBSP0_X,
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DM365_MCBSP0_BFSX,
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DM365_MCBSP0_BDR,
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DM365_MCBSP0_R,
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DM365_MCBSP0_BFSR,
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/* SPI0 */
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DM365_SPI0_SCLK,
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DM365_SPI0_SDI,
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DM365_SPI0_SDO,
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DM365_SPI0_SDENA0,
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DM365_SPI0_SDENA1,
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/* UART */
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DM365_UART0_RXD,
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DM365_UART0_TXD,
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DM365_UART1_RXD,
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DM365_UART1_TXD,
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DM365_UART1_RTS,
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DM365_UART1_CTS,
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/* EMAC */
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DM365_EMAC_TX_EN,
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DM365_EMAC_TX_CLK,
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DM365_EMAC_COL,
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DM365_EMAC_TXD3,
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DM365_EMAC_TXD2,
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DM365_EMAC_TXD1,
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DM365_EMAC_TXD0,
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DM365_EMAC_RXD3,
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DM365_EMAC_RXD2,
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DM365_EMAC_RXD1,
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DM365_EMAC_RXD0,
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DM365_EMAC_RX_CLK,
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DM365_EMAC_RX_DV,
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DM365_EMAC_RX_ER,
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DM365_EMAC_CRS,
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DM365_EMAC_MDIO,
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DM365_EMAC_MDCLK,
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/* IRQ muxing */
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DM365_INT_EDMA_CC,
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DM365_INT_EDMA_TC0_ERR,
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DM365_INT_EDMA_TC1_ERR,
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DM365_INT_PRTCSS,
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DM365_INT_EMAC_RXTHRESH,
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DM365_INT_EMAC_RXPULSE,
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DM365_INT_EMAC_TXPULSE,
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DM365_INT_EMAC_MISCPULSE,
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/* EDMA event muxing */
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DM365_EVT2_ASP_TX,
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DM365_EVT3_ASP_RX,
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DM365_EVT26_MMC0_RX,
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};
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#ifdef CONFIG_DAVINCI_MUX
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/* setup pin muxing */
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extern int davinci_cfg_reg(unsigned long reg_cfg);
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#else
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/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
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static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
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#endif
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#endif /* __INC_MACH_MUX_H */
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