d6ff7d0fe2
This adds drivers for the LCD controller found in VIA VT8500 SoC, GOVR display controller found in WonderMedia WM8505 SoC and for the Graphics Engine present in both of them that provides hardware accelerated raster operations (used for copyarea and fillrect). Signed-off-by: Alexey Charkov <alchark@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
76 lines
2.1 KiB
C
76 lines
2.1 KiB
C
/*
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* GOVR registers list for WM8505 chips
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*
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* Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com>
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* Based on VIA/WonderMedia wm8510-govrh-reg.h
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* http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/
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* drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _WM8505FB_REGS_H
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#define _WM8505FB_REGS_H
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/*
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* Color space select register, default value 0x1c
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* BIT0 GOVRH_DVO_YUV2RGB_ENABLE
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* BIT1 GOVRH_VGA_YUV2RGB_ENABLE
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* BIT2 GOVRH_RGB_MODE
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* BIT3 GOVRH_DAC_CLKINV
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* BIT4 GOVRH_BLANK_ZERO
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*/
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#define WMT_GOVR_COLORSPACE 0x1e4
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/*
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* Another colorspace select register, default value 1
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* BIT0 GOVRH_DVO_RGB
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* BIT1 GOVRH_DVO_YUV422
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*/
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#define WMT_GOVR_COLORSPACE1 0x30
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#define WMT_GOVR_CONTRAST 0x1b8
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#define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
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/* Framubeffer address */
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#define WMT_GOVR_FBADDR 0x90
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#define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
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/* Offset of visible window */
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#define WMT_GOVR_XPAN 0xa4
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#define WMT_GOVR_YPAN 0xa0
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#define WMT_GOVR_XRES 0x98
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#define WMT_GOVR_XRES_VIRTUAL 0x9c
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#define WMT_GOVR_MIF_ENABLE 0x80
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#define WMT_GOVR_FHI 0xa8
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#define WMT_GOVR_REG_UPDATE 0xe4
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/*
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* BIT0 GOVRH_DVO_OUTWIDTH
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* BIT1 GOVRH_DVO_SYNC_POLAR
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* BIT2 GOVRH_DVO_ENABLE
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*/
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#define WMT_GOVR_DVO_SET 0x148
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/* Timing generator? */
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#define WMT_GOVR_TG 0x100
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/* Timings */
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#define WMT_GOVR_TIMING_H_ALL 0x108
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#define WMT_GOVR_TIMING_V_ALL 0x10c
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#define WMT_GOVR_TIMING_V_START 0x110
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#define WMT_GOVR_TIMING_V_END 0x114
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#define WMT_GOVR_TIMING_H_START 0x118
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#define WMT_GOVR_TIMING_H_END 0x11c
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#define WMT_GOVR_TIMING_V_SYNC 0x128
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#define WMT_GOVR_TIMING_H_SYNC 0x12c
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#endif /* _WM8505FB_REGS_H */
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