1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
713 lines
16 KiB
C
713 lines
16 KiB
C
/*
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* arch/ppc64/kernel/xics.c
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*
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* Copyright 2000 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/threads.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/signal.h>
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#include <linux/init.h>
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#include <linux/gfp.h>
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#include <linux/radix-tree.h>
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#include <linux/cpu.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/rtas.h>
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#include <asm/xics.h>
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#include <asm/hvcall.h>
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#include <asm/machdep.h>
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#include "i8259.h"
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static unsigned int xics_startup(unsigned int irq);
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static void xics_enable_irq(unsigned int irq);
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static void xics_disable_irq(unsigned int irq);
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static void xics_mask_and_ack_irq(unsigned int irq);
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static void xics_end_irq(unsigned int irq);
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static void xics_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
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struct hw_interrupt_type xics_pic = {
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.typename = " XICS ",
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.startup = xics_startup,
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.enable = xics_enable_irq,
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.disable = xics_disable_irq,
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.ack = xics_mask_and_ack_irq,
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.end = xics_end_irq,
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.set_affinity = xics_set_affinity
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};
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struct hw_interrupt_type xics_8259_pic = {
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.typename = " XICS/8259",
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.ack = xics_mask_and_ack_irq,
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};
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/* This is used to map real irq numbers to virtual */
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static struct radix_tree_root irq_map = RADIX_TREE_INIT(GFP_ATOMIC);
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#define XICS_IPI 2
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#define XICS_IRQ_SPURIOUS 0
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/* Want a priority other than 0. Various HW issues require this. */
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#define DEFAULT_PRIORITY 5
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/*
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* Mark IPIs as higher priority so we can take them inside interrupts that
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* arent marked SA_INTERRUPT
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*/
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#define IPI_PRIORITY 4
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struct xics_ipl {
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union {
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u32 word;
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u8 bytes[4];
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} xirr_poll;
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union {
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u32 word;
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u8 bytes[4];
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} xirr;
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u32 dummy;
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union {
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u32 word;
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u8 bytes[4];
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} qirr;
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};
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static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
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static int xics_irq_8259_cascade = 0;
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static int xics_irq_8259_cascade_real = 0;
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static unsigned int default_server = 0xFF;
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/* also referenced in smp.c... */
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unsigned int default_distrib_server = 0;
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unsigned int interrupt_server_size = 8;
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/*
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* XICS only has a single IPI, so encode the messages per CPU
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*/
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struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
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/* RTAS service tokens */
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int ibm_get_xive;
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int ibm_set_xive;
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int ibm_int_on;
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int ibm_int_off;
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typedef struct {
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int (*xirr_info_get)(int cpu);
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void (*xirr_info_set)(int cpu, int val);
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void (*cppr_info)(int cpu, u8 val);
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void (*qirr_info)(int cpu, u8 val);
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} xics_ops;
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/* SMP */
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static int pSeries_xirr_info_get(int n_cpu)
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{
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return in_be32(&xics_per_cpu[n_cpu]->xirr.word);
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}
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static void pSeries_xirr_info_set(int n_cpu, int value)
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{
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out_be32(&xics_per_cpu[n_cpu]->xirr.word, value);
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}
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static void pSeries_cppr_info(int n_cpu, u8 value)
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{
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out_8(&xics_per_cpu[n_cpu]->xirr.bytes[0], value);
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}
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static void pSeries_qirr_info(int n_cpu, u8 value)
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{
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out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
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}
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static xics_ops pSeries_ops = {
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pSeries_xirr_info_get,
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pSeries_xirr_info_set,
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pSeries_cppr_info,
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pSeries_qirr_info
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};
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static xics_ops *ops = &pSeries_ops;
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/* LPAR */
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static inline long plpar_eoi(unsigned long xirr)
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{
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return plpar_hcall_norets(H_EOI, xirr);
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}
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static inline long plpar_cppr(unsigned long cppr)
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{
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return plpar_hcall_norets(H_CPPR, cppr);
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}
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static inline long plpar_ipi(unsigned long servernum, unsigned long mfrr)
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{
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return plpar_hcall_norets(H_IPI, servernum, mfrr);
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}
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static inline long plpar_xirr(unsigned long *xirr_ret)
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{
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unsigned long dummy;
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return plpar_hcall(H_XIRR, 0, 0, 0, 0, xirr_ret, &dummy, &dummy);
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}
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static int pSeriesLP_xirr_info_get(int n_cpu)
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{
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unsigned long lpar_rc;
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unsigned long return_value;
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lpar_rc = plpar_xirr(&return_value);
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if (lpar_rc != H_Success)
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panic(" bad return code xirr - rc = %lx \n", lpar_rc);
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return (int)return_value;
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}
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static void pSeriesLP_xirr_info_set(int n_cpu, int value)
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{
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unsigned long lpar_rc;
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unsigned long val64 = value & 0xffffffff;
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lpar_rc = plpar_eoi(val64);
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if (lpar_rc != H_Success)
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panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc,
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val64);
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}
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void pSeriesLP_cppr_info(int n_cpu, u8 value)
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{
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unsigned long lpar_rc;
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lpar_rc = plpar_cppr(value);
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if (lpar_rc != H_Success)
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panic("bad return code cppr - rc = %lx\n", lpar_rc);
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}
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static void pSeriesLP_qirr_info(int n_cpu , u8 value)
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{
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unsigned long lpar_rc;
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lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
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if (lpar_rc != H_Success)
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panic("bad return code qirr - rc = %lx\n", lpar_rc);
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}
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xics_ops pSeriesLP_ops = {
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pSeriesLP_xirr_info_get,
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pSeriesLP_xirr_info_set,
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pSeriesLP_cppr_info,
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pSeriesLP_qirr_info
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};
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static unsigned int xics_startup(unsigned int virq)
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{
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unsigned int irq;
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irq = irq_offset_down(virq);
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if (radix_tree_insert(&irq_map, virt_irq_to_real(irq),
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&virt_irq_to_real_map[irq]) == -ENOMEM)
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printk(KERN_CRIT "Out of memory creating real -> virtual"
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" IRQ mapping for irq %u (real 0x%x)\n",
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virq, virt_irq_to_real(irq));
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xics_enable_irq(virq);
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return 0; /* return value is ignored */
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}
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static unsigned int real_irq_to_virt(unsigned int real_irq)
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{
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unsigned int *ptr;
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ptr = radix_tree_lookup(&irq_map, real_irq);
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if (ptr == NULL)
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return NO_IRQ;
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return ptr - virt_irq_to_real_map;
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}
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#ifdef CONFIG_SMP
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static int get_irq_server(unsigned int irq)
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{
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unsigned int server;
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/* For the moment only implement delivery to all cpus or one cpu */
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cpumask_t cpumask = irq_affinity[irq];
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cpumask_t tmp = CPU_MASK_NONE;
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if (!distribute_irqs)
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return default_server;
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if (cpus_equal(cpumask, CPU_MASK_ALL)) {
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server = default_distrib_server;
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} else {
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cpus_and(tmp, cpu_online_map, cpumask);
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if (cpus_empty(tmp))
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server = default_distrib_server;
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else
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server = get_hard_smp_processor_id(first_cpu(tmp));
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}
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return server;
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}
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#else
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static int get_irq_server(unsigned int irq)
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{
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return default_server;
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}
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#endif
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static void xics_enable_irq(unsigned int virq)
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{
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unsigned int irq;
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int call_status;
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unsigned int server;
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irq = virt_irq_to_real(irq_offset_down(virq));
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if (irq == XICS_IPI)
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return;
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server = get_irq_server(virq);
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call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
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DEFAULT_PRIORITY);
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if (call_status != 0) {
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printk(KERN_ERR "xics_enable_irq: irq=%d: ibm_set_xive "
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"returned %x\n", irq, call_status);
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return;
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}
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/* Now unmask the interrupt (often a no-op) */
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call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
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if (call_status != 0) {
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printk(KERN_ERR "xics_enable_irq: irq=%d: ibm_int_on "
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"returned %x\n", irq, call_status);
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return;
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}
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}
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static void xics_disable_real_irq(unsigned int irq)
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{
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int call_status;
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unsigned int server;
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if (irq == XICS_IPI)
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return;
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call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
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if (call_status != 0) {
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printk(KERN_ERR "xics_disable_real_irq: irq=%d: "
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"ibm_int_off returned %x\n", irq, call_status);
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return;
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}
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server = get_irq_server(irq);
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/* Have to set XIVE to 0xff to be able to remove a slot */
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call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, 0xff);
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if (call_status != 0) {
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printk(KERN_ERR "xics_disable_irq: irq=%d: ibm_set_xive(0xff)"
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" returned %x\n", irq, call_status);
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return;
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}
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}
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static void xics_disable_irq(unsigned int virq)
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{
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unsigned int irq;
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irq = virt_irq_to_real(irq_offset_down(virq));
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xics_disable_real_irq(irq);
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}
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static void xics_end_irq(unsigned int irq)
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{
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int cpu = smp_processor_id();
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iosync();
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ops->xirr_info_set(cpu, ((0xff << 24) |
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(virt_irq_to_real(irq_offset_down(irq)))));
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}
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static void xics_mask_and_ack_irq(unsigned int irq)
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{
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int cpu = smp_processor_id();
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if (irq < irq_offset_value()) {
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i8259_pic.ack(irq);
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iosync();
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ops->xirr_info_set(cpu, ((0xff<<24) |
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xics_irq_8259_cascade_real));
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iosync();
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}
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}
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int xics_get_irq(struct pt_regs *regs)
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{
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unsigned int cpu = smp_processor_id();
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unsigned int vec;
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int irq;
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vec = ops->xirr_info_get(cpu);
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/* (vec >> 24) == old priority */
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vec &= 0x00ffffff;
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/* for sanity, this had better be < NR_IRQS - 16 */
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if (vec == xics_irq_8259_cascade_real) {
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irq = i8259_irq(cpu);
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if (irq == -1) {
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/* Spurious cascaded interrupt. Still must ack xics */
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xics_end_irq(irq_offset_up(xics_irq_8259_cascade));
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irq = -1;
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}
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} else if (vec == XICS_IRQ_SPURIOUS) {
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irq = -1;
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} else {
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irq = real_irq_to_virt(vec);
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if (irq == NO_IRQ)
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irq = real_irq_to_virt_slowpath(vec);
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if (irq == NO_IRQ) {
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printk(KERN_ERR "Interrupt %d (real) is invalid,"
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" disabling it.\n", vec);
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xics_disable_real_irq(vec);
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} else
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irq = irq_offset_up(irq);
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}
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return irq;
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}
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#ifdef CONFIG_SMP
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irqreturn_t xics_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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ops->qirr_info(cpu, 0xff);
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WARN_ON(cpu_is_offline(cpu));
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while (xics_ipi_message[cpu].value) {
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if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_CALL_FUNCTION, regs);
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}
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if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_RESCHEDULE, regs);
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}
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#if 0
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if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_MIGRATE_TASK, regs);
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}
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#endif
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#ifdef CONFIG_DEBUGGER
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if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_DEBUGGER_BREAK, regs);
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}
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#endif
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}
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return IRQ_HANDLED;
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}
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void xics_cause_IPI(int cpu)
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{
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ops->qirr_info(cpu, IPI_PRIORITY);
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}
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void xics_setup_cpu(void)
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{
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int cpu = smp_processor_id();
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ops->cppr_info(cpu, 0xff);
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iosync();
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}
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#endif /* CONFIG_SMP */
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void xics_init_IRQ(void)
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{
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int i;
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unsigned long intr_size = 0;
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struct device_node *np;
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uint *ireg, ilen, indx = 0;
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unsigned long intr_base = 0;
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struct xics_interrupt_node {
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unsigned long addr;
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unsigned long size;
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} intnodes[NR_CPUS];
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ppc64_boot_msg(0x20, "XICS Init");
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ibm_get_xive = rtas_token("ibm,get-xive");
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ibm_set_xive = rtas_token("ibm,set-xive");
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ibm_int_on = rtas_token("ibm,int-on");
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ibm_int_off = rtas_token("ibm,int-off");
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np = of_find_node_by_type(NULL, "PowerPC-External-Interrupt-Presentation");
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if (!np)
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panic("xics_init_IRQ: can't find interrupt presentation");
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nextnode:
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ireg = (uint *)get_property(np, "ibm,interrupt-server-ranges", NULL);
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if (ireg) {
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/*
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* set node starting index for this node
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*/
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indx = *ireg;
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}
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ireg = (uint *)get_property(np, "reg", &ilen);
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if (!ireg)
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panic("xics_init_IRQ: can't find interrupt reg property");
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while (ilen) {
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intnodes[indx].addr = (unsigned long)*ireg++ << 32;
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ilen -= sizeof(uint);
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intnodes[indx].addr |= *ireg++;
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ilen -= sizeof(uint);
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intnodes[indx].size = (unsigned long)*ireg++ << 32;
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ilen -= sizeof(uint);
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intnodes[indx].size |= *ireg++;
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ilen -= sizeof(uint);
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indx++;
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if (indx >= NR_CPUS) break;
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}
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np = of_find_node_by_type(np, "PowerPC-External-Interrupt-Presentation");
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if ((indx < NR_CPUS) && np) goto nextnode;
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/* Find the server numbers for the boot cpu. */
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for (np = of_find_node_by_type(NULL, "cpu");
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np;
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np = of_find_node_by_type(np, "cpu")) {
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ireg = (uint *)get_property(np, "reg", &ilen);
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if (ireg && ireg[0] == boot_cpuid_phys) {
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ireg = (uint *)get_property(np, "ibm,ppc-interrupt-gserver#s",
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&ilen);
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i = ilen / sizeof(int);
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if (ireg && i > 0) {
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default_server = ireg[0];
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default_distrib_server = ireg[i-1]; /* take last element */
|
|
}
|
|
ireg = (uint *)get_property(np,
|
|
"ibm,interrupt-server#-size", NULL);
|
|
if (ireg)
|
|
interrupt_server_size = *ireg;
|
|
break;
|
|
}
|
|
}
|
|
of_node_put(np);
|
|
|
|
intr_base = intnodes[0].addr;
|
|
intr_size = intnodes[0].size;
|
|
|
|
np = of_find_node_by_type(NULL, "interrupt-controller");
|
|
if (!np) {
|
|
printk(KERN_WARNING "xics: no ISA interrupt controller\n");
|
|
xics_irq_8259_cascade_real = -1;
|
|
xics_irq_8259_cascade = -1;
|
|
} else {
|
|
ireg = (uint *) get_property(np, "interrupts", NULL);
|
|
if (!ireg)
|
|
panic("xics_init_IRQ: can't find ISA interrupts property");
|
|
|
|
xics_irq_8259_cascade_real = *ireg;
|
|
xics_irq_8259_cascade
|
|
= virt_irq_create_mapping(xics_irq_8259_cascade_real);
|
|
of_node_put(np);
|
|
}
|
|
|
|
if (systemcfg->platform == PLATFORM_PSERIES) {
|
|
#ifdef CONFIG_SMP
|
|
for_each_cpu(i) {
|
|
int hard_id;
|
|
|
|
/* FIXME: Do this dynamically! --RR */
|
|
if (!cpu_present(i))
|
|
continue;
|
|
|
|
hard_id = get_hard_smp_processor_id(i);
|
|
xics_per_cpu[i] = ioremap(intnodes[hard_id].addr,
|
|
intnodes[hard_id].size);
|
|
}
|
|
#else
|
|
xics_per_cpu[0] = ioremap(intr_base, intr_size);
|
|
#endif /* CONFIG_SMP */
|
|
} else if (systemcfg->platform == PLATFORM_PSERIES_LPAR) {
|
|
ops = &pSeriesLP_ops;
|
|
}
|
|
|
|
xics_8259_pic.enable = i8259_pic.enable;
|
|
xics_8259_pic.disable = i8259_pic.disable;
|
|
for (i = 0; i < 16; ++i)
|
|
get_irq_desc(i)->handler = &xics_8259_pic;
|
|
for (; i < NR_IRQS; ++i)
|
|
get_irq_desc(i)->handler = &xics_pic;
|
|
|
|
ops->cppr_info(boot_cpuid, 0xff);
|
|
iosync();
|
|
|
|
ppc64_boot_msg(0x21, "XICS Done");
|
|
}
|
|
|
|
/*
|
|
* We cant do this in init_IRQ because we need the memory subsystem up for
|
|
* request_irq()
|
|
*/
|
|
static int __init xics_setup_i8259(void)
|
|
{
|
|
if (ppc64_interrupt_controller == IC_PPC_XIC &&
|
|
xics_irq_8259_cascade != -1) {
|
|
if (request_irq(irq_offset_up(xics_irq_8259_cascade),
|
|
no_action, 0, "8259 cascade", NULL))
|
|
printk(KERN_ERR "xics_setup_i8259: couldn't get 8259 "
|
|
"cascade\n");
|
|
i8259_init(0);
|
|
}
|
|
return 0;
|
|
}
|
|
arch_initcall(xics_setup_i8259);
|
|
|
|
#ifdef CONFIG_SMP
|
|
void xics_request_IPIs(void)
|
|
{
|
|
virt_irq_to_real_map[XICS_IPI] = XICS_IPI;
|
|
|
|
/* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
|
|
request_irq(irq_offset_up(XICS_IPI), xics_ipi_action, SA_INTERRUPT,
|
|
"IPI", NULL);
|
|
get_irq_desc(irq_offset_up(XICS_IPI))->status |= IRQ_PER_CPU;
|
|
}
|
|
#endif
|
|
|
|
static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
|
|
{
|
|
unsigned int irq;
|
|
int status;
|
|
int xics_status[2];
|
|
unsigned long newmask;
|
|
cpumask_t tmp = CPU_MASK_NONE;
|
|
|
|
irq = virt_irq_to_real(irq_offset_down(virq));
|
|
if (irq == XICS_IPI || irq == NO_IRQ)
|
|
return;
|
|
|
|
status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
|
|
|
|
if (status) {
|
|
printk(KERN_ERR "xics_set_affinity: irq=%d ibm,get-xive "
|
|
"returns %d\n", irq, status);
|
|
return;
|
|
}
|
|
|
|
/* For the moment only implement delivery to all cpus or one cpu */
|
|
if (cpus_equal(cpumask, CPU_MASK_ALL)) {
|
|
newmask = default_distrib_server;
|
|
} else {
|
|
cpus_and(tmp, cpu_online_map, cpumask);
|
|
if (cpus_empty(tmp))
|
|
return;
|
|
newmask = get_hard_smp_processor_id(first_cpu(tmp));
|
|
}
|
|
|
|
status = rtas_call(ibm_set_xive, 3, 1, NULL,
|
|
irq, newmask, xics_status[1]);
|
|
|
|
if (status) {
|
|
printk(KERN_ERR "xics_set_affinity: irq=%d ibm,set-xive "
|
|
"returns %d\n", irq, status);
|
|
return;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
/* Interrupts are disabled. */
|
|
void xics_migrate_irqs_away(void)
|
|
{
|
|
int status;
|
|
unsigned int irq, virq, cpu = smp_processor_id();
|
|
|
|
/* Reject any interrupt that was queued to us... */
|
|
ops->cppr_info(cpu, 0);
|
|
iosync();
|
|
|
|
/* remove ourselves from the global interrupt queue */
|
|
status = rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
|
|
(1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
|
|
WARN_ON(status < 0);
|
|
|
|
/* Allow IPIs again... */
|
|
ops->cppr_info(cpu, DEFAULT_PRIORITY);
|
|
iosync();
|
|
|
|
for_each_irq(virq) {
|
|
irq_desc_t *desc;
|
|
int xics_status[2];
|
|
unsigned long flags;
|
|
|
|
/* We cant set affinity on ISA interrupts */
|
|
if (virq < irq_offset_value())
|
|
continue;
|
|
|
|
desc = get_irq_desc(virq);
|
|
irq = virt_irq_to_real(irq_offset_down(virq));
|
|
|
|
/* We need to get IPIs still. */
|
|
if (irq == XICS_IPI || irq == NO_IRQ)
|
|
continue;
|
|
|
|
/* We only need to migrate enabled IRQS */
|
|
if (desc == NULL || desc->handler == NULL
|
|
|| desc->action == NULL
|
|
|| desc->handler->set_affinity == NULL)
|
|
continue;
|
|
|
|
spin_lock_irqsave(&desc->lock, flags);
|
|
|
|
status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
|
|
if (status) {
|
|
printk(KERN_ERR "migrate_irqs_away: irq=%d "
|
|
"ibm,get-xive returns %d\n",
|
|
virq, status);
|
|
goto unlock;
|
|
}
|
|
|
|
/*
|
|
* We only support delivery to all cpus or to one cpu.
|
|
* The irq has to be migrated only in the single cpu
|
|
* case.
|
|
*/
|
|
if (xics_status[0] != get_hard_smp_processor_id(cpu))
|
|
goto unlock;
|
|
|
|
printk(KERN_WARNING "IRQ %d affinity broken off cpu %u\n",
|
|
virq, cpu);
|
|
|
|
/* Reset affinity to all cpus */
|
|
desc->handler->set_affinity(virq, CPU_MASK_ALL);
|
|
irq_affinity[virq] = CPU_MASK_ALL;
|
|
unlock:
|
|
spin_unlock_irqrestore(&desc->lock, flags);
|
|
}
|
|
}
|
|
#endif
|