e2eb63927b
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
748 lines
21 KiB
C
748 lines
21 KiB
C
/*
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* IOMMU implementation for Cell Broadband Processor Architecture
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*
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* (C) Copyright IBM Corporation 2006
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*
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* Author: Jeremy Kerr <jk@ozlabs.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/notifier.h>
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#include <asm/prom.h>
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#include <asm/iommu.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/udbg.h>
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#include <asm/of_platform.h>
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#include <asm/lmb.h>
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#include "cbe_regs.h"
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#include "interrupt.h"
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/* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
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* instead of leaving them mapped to some dummy page. This can be
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* enabled once the appropriate workarounds for spider bugs have
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* been enabled
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*/
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#define CELL_IOMMU_REAL_UNMAP
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/* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of
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* IO PTEs based on the transfer direction. That can be enabled
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* once spider-net has been fixed to pass the correct direction
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* to the DMA mapping functions
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*/
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#define CELL_IOMMU_STRICT_PROTECTION
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#define NR_IOMMUS 2
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/* IOC mmap registers */
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#define IOC_Reg_Size 0x2000
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#define IOC_IOPT_CacheInvd 0x908
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#define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul
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#define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul
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#define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul
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#define IOC_IOST_Origin 0x918
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#define IOC_IOST_Origin_E 0x8000000000000000ul
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#define IOC_IOST_Origin_HW 0x0000000000000800ul
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#define IOC_IOST_Origin_HL 0x0000000000000400ul
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#define IOC_IO_ExcpStat 0x920
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#define IOC_IO_ExcpStat_V 0x8000000000000000ul
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#define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul
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#define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul
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#define IOC_IO_ExcpStat_SPF_P 0x4000000000000000ul
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#define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul
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#define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul
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#define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful
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#define IOC_IO_ExcpMask 0x928
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#define IOC_IO_ExcpMask_SFE 0x4000000000000000ul
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#define IOC_IO_ExcpMask_PFE 0x2000000000000000ul
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#define IOC_IOCmd_Offset 0x1000
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#define IOC_IOCmd_Cfg 0xc00
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#define IOC_IOCmd_Cfg_TE 0x0000800000000000ul
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/* Segment table entries */
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#define IOSTE_V 0x8000000000000000ul /* valid */
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#define IOSTE_H 0x4000000000000000ul /* cache hint */
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#define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */
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#define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */
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#define IOSTE_PS_Mask 0x0000000000000007ul /* page size */
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#define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */
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#define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */
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#define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */
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#define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */
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/* Page table entries */
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#define IOPTE_PP_W 0x8000000000000000ul /* protection: write */
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#define IOPTE_PP_R 0x4000000000000000ul /* protection: read */
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#define IOPTE_M 0x2000000000000000ul /* coherency required */
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#define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */
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#define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */
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#define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */
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#define IOPTE_H 0x0000000000000800ul /* cache hint */
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#define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */
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/* IOMMU sizing */
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#define IO_SEGMENT_SHIFT 28
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#define IO_PAGENO_BITS (IO_SEGMENT_SHIFT - IOMMU_PAGE_SHIFT)
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/* The high bit needs to be set on every DMA address */
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#define SPIDER_DMA_OFFSET 0x80000000ul
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struct iommu_window {
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struct list_head list;
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struct cbe_iommu *iommu;
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unsigned long offset;
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unsigned long size;
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unsigned long pte_offset;
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unsigned int ioid;
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struct iommu_table table;
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};
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#define NAMESIZE 8
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struct cbe_iommu {
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int nid;
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char name[NAMESIZE];
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void __iomem *xlate_regs;
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void __iomem *cmd_regs;
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unsigned long *stab;
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unsigned long *ptab;
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void *pad_page;
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struct list_head windows;
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};
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/* Static array of iommus, one per node
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* each contains a list of windows, keyed from dma_window property
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* - on bus setup, look for a matching window, or create one
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* - on dev setup, assign iommu_table ptr
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*/
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static struct cbe_iommu iommus[NR_IOMMUS];
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static int cbe_nr_iommus;
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static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
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long n_ptes)
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{
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unsigned long __iomem *reg;
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unsigned long val;
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long n;
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reg = iommu->xlate_regs + IOC_IOPT_CacheInvd;
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while (n_ptes > 0) {
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/* we can invalidate up to 1 << 11 PTEs at once */
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n = min(n_ptes, 1l << 11);
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val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask)
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| (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask)
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| IOC_IOPT_CacheInvd_Busy;
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out_be64(reg, val);
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while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy)
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;
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n_ptes -= n;
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pte += n;
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}
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}
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static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
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unsigned long uaddr, enum dma_data_direction direction)
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{
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int i;
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unsigned long *io_pte, base_pte;
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struct iommu_window *window =
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container_of(tbl, struct iommu_window, table);
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/* implementing proper protection causes problems with the spidernet
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* driver - check mapping directions later, but allow read & write by
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* default for now.*/
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#ifdef CELL_IOMMU_STRICT_PROTECTION
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/* to avoid referencing a global, we use a trick here to setup the
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* protection bit. "prot" is setup to be 3 fields of 4 bits apprended
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* together for each of the 3 supported direction values. It is then
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* shifted left so that the fields matching the desired direction
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* lands on the appropriate bits, and other bits are masked out.
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*/
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const unsigned long prot = 0xc48;
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base_pte =
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((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R))
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| IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask);
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#else
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base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW |
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(window->ioid & IOPTE_IOID_Mask);
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#endif
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io_pte = (unsigned long *)tbl->it_base + (index - window->pte_offset);
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for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE)
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io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask);
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mb();
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invalidate_tce_cache(window->iommu, io_pte, npages);
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pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n",
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index, npages, direction, base_pte);
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}
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static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
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{
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int i;
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unsigned long *io_pte, pte;
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struct iommu_window *window =
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container_of(tbl, struct iommu_window, table);
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pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages);
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#ifdef CELL_IOMMU_REAL_UNMAP
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pte = 0;
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#else
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/* spider bridge does PCI reads after freeing - insert a mapping
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* to a scratch page instead of an invalid entry */
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pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page)
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| (window->ioid & IOPTE_IOID_Mask);
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#endif
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io_pte = (unsigned long *)tbl->it_base + (index - window->pte_offset);
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for (i = 0; i < npages; i++)
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io_pte[i] = pte;
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mb();
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invalidate_tce_cache(window->iommu, io_pte, npages);
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}
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static irqreturn_t ioc_interrupt(int irq, void *data)
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{
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unsigned long stat;
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struct cbe_iommu *iommu = data;
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stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
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/* Might want to rate limit it */
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printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat);
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printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n",
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!!(stat & IOC_IO_ExcpStat_V),
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(stat & IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ',
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(stat & IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ',
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(stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write",
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(unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask));
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printk(KERN_ERR " page=0x%016lx\n",
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stat & IOC_IO_ExcpStat_ADDR_Mask);
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/* clear interrupt */
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stat &= ~IOC_IO_ExcpStat_V;
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out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat);
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return IRQ_HANDLED;
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}
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static int cell_iommu_find_ioc(int nid, unsigned long *base)
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{
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struct device_node *np;
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struct resource r;
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*base = 0;
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/* First look for new style /be nodes */
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for_each_node_by_name(np, "ioc") {
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if (of_node_to_nid(np) != nid)
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continue;
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "iommu: can't get address for %s\n",
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np->full_name);
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continue;
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}
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*base = r.start;
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of_node_put(np);
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return 0;
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}
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/* Ok, let's try the old way */
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for_each_node_by_type(np, "cpu") {
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const unsigned int *nidp;
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const unsigned long *tmp;
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nidp = of_get_property(np, "node-id", NULL);
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if (nidp && *nidp == nid) {
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tmp = of_get_property(np, "ioc-translation", NULL);
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if (tmp) {
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*base = *tmp;
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of_node_put(np);
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return 0;
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}
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}
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}
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return -ENODEV;
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}
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static void cell_iommu_setup_hardware(struct cbe_iommu *iommu, unsigned long size)
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{
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struct page *page;
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int ret, i;
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unsigned long reg, segments, pages_per_segment, ptab_size, n_pte_pages;
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unsigned long xlate_base;
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unsigned int virq;
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if (cell_iommu_find_ioc(iommu->nid, &xlate_base))
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panic("%s: missing IOC register mappings for node %d\n",
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__FUNCTION__, iommu->nid);
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iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size);
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iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset;
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segments = size >> IO_SEGMENT_SHIFT;
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pages_per_segment = 1ull << IO_PAGENO_BITS;
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pr_debug("%s: iommu[%d]: segments: %lu, pages per segment: %lu\n",
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__FUNCTION__, iommu->nid, segments, pages_per_segment);
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/* set up the segment table */
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page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
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BUG_ON(!page);
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iommu->stab = page_address(page);
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clear_page(iommu->stab);
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/* ... and the page tables. Since these are contiguous, we can treat
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* the page tables as one array of ptes, like pSeries does.
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*/
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ptab_size = segments * pages_per_segment * sizeof(unsigned long);
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pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __FUNCTION__,
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iommu->nid, ptab_size, get_order(ptab_size));
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page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
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BUG_ON(!page);
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iommu->ptab = page_address(page);
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memset(iommu->ptab, 0, ptab_size);
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/* allocate a bogus page for the end of each mapping */
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page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
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BUG_ON(!page);
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iommu->pad_page = page_address(page);
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clear_page(iommu->pad_page);
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/* number of pages needed for a page table */
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n_pte_pages = (pages_per_segment *
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sizeof(unsigned long)) >> IOMMU_PAGE_SHIFT;
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pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
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__FUNCTION__, iommu->nid, iommu->stab, iommu->ptab,
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n_pte_pages);
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/* initialise the STEs */
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reg = IOSTE_V | ((n_pte_pages - 1) << 5);
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if (IOMMU_PAGE_SIZE == 0x1000)
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reg |= IOSTE_PS_4K;
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else if (IOMMU_PAGE_SIZE == 0x10000)
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reg |= IOSTE_PS_64K;
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else {
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extern void __unknown_page_size_error(void);
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__unknown_page_size_error();
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}
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pr_debug("Setting up IOMMU stab:\n");
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for (i = 0; i * (1ul << IO_SEGMENT_SHIFT) < size; i++) {
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iommu->stab[i] = reg |
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(__pa(iommu->ptab) + n_pte_pages * IOMMU_PAGE_SIZE * i);
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pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]);
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}
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/* ensure that the STEs have updated */
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mb();
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/* setup interrupts for the iommu. */
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reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
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out_be64(iommu->xlate_regs + IOC_IO_ExcpStat,
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reg & ~IOC_IO_ExcpStat_V);
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out_be64(iommu->xlate_regs + IOC_IO_ExcpMask,
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IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE);
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virq = irq_create_mapping(NULL,
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IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT));
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BUG_ON(virq == NO_IRQ);
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ret = request_irq(virq, ioc_interrupt, IRQF_DISABLED,
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iommu->name, iommu);
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BUG_ON(ret);
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/* set the IOC segment table origin register (and turn on the iommu) */
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reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW;
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out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg);
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in_be64(iommu->xlate_regs + IOC_IOST_Origin);
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/* turn on IO translation */
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reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE;
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out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg);
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}
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#if 0/* Unused for now */
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static struct iommu_window *find_window(struct cbe_iommu *iommu,
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unsigned long offset, unsigned long size)
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{
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struct iommu_window *window;
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/* todo: check for overlapping (but not equal) windows) */
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list_for_each_entry(window, &(iommu->windows), list) {
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if (window->offset == offset && window->size == size)
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return window;
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}
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return NULL;
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}
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#endif
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static struct iommu_window * __init
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cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
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unsigned long offset, unsigned long size,
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unsigned long pte_offset)
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{
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struct iommu_window *window;
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const unsigned int *ioid;
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ioid = of_get_property(np, "ioid", NULL);
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if (ioid == NULL)
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printk(KERN_WARNING "iommu: missing ioid for %s using 0\n",
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np->full_name);
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window = kmalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid);
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BUG_ON(window == NULL);
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window->offset = offset;
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window->size = size;
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window->ioid = ioid ? *ioid : 0;
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window->iommu = iommu;
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window->pte_offset = pte_offset;
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window->table.it_blocksize = 16;
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window->table.it_base = (unsigned long)iommu->ptab;
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window->table.it_index = iommu->nid;
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window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) +
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window->pte_offset;
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window->table.it_size = size >> IOMMU_PAGE_SHIFT;
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iommu_init_table(&window->table, iommu->nid);
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|
|
pr_debug("\tioid %d\n", window->ioid);
|
|
pr_debug("\tblocksize %ld\n", window->table.it_blocksize);
|
|
pr_debug("\tbase 0x%016lx\n", window->table.it_base);
|
|
pr_debug("\toffset 0x%lx\n", window->table.it_offset);
|
|
pr_debug("\tsize %ld\n", window->table.it_size);
|
|
|
|
list_add(&window->list, &iommu->windows);
|
|
|
|
if (offset != 0)
|
|
return window;
|
|
|
|
/* We need to map and reserve the first IOMMU page since it's used
|
|
* by the spider workaround. In theory, we only need to do that when
|
|
* running on spider but it doesn't really matter.
|
|
*
|
|
* This code also assumes that we have a window that starts at 0,
|
|
* which is the case on all spider based blades.
|
|
*/
|
|
__set_bit(0, window->table.it_map);
|
|
tce_build_cell(&window->table, window->table.it_offset, 1,
|
|
(unsigned long)iommu->pad_page, DMA_TO_DEVICE);
|
|
window->table.it_hint = window->table.it_blocksize;
|
|
|
|
return window;
|
|
}
|
|
|
|
static struct cbe_iommu *cell_iommu_for_node(int nid)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < cbe_nr_iommus; i++)
|
|
if (iommus[i].nid == nid)
|
|
return &iommus[i];
|
|
return NULL;
|
|
}
|
|
|
|
static void cell_dma_dev_setup(struct device *dev)
|
|
{
|
|
struct iommu_window *window;
|
|
struct cbe_iommu *iommu;
|
|
struct dev_archdata *archdata = &dev->archdata;
|
|
|
|
/* If we run without iommu, no need to do anything */
|
|
if (get_pci_dma_ops() == &dma_direct_ops)
|
|
return;
|
|
|
|
/* Current implementation uses the first window available in that
|
|
* node's iommu. We -might- do something smarter later though it may
|
|
* never be necessary
|
|
*/
|
|
iommu = cell_iommu_for_node(archdata->numa_node);
|
|
if (iommu == NULL || list_empty(&iommu->windows)) {
|
|
printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n",
|
|
archdata->of_node ? archdata->of_node->full_name : "?",
|
|
archdata->numa_node);
|
|
return;
|
|
}
|
|
window = list_entry(iommu->windows.next, struct iommu_window, list);
|
|
|
|
archdata->dma_data = &window->table;
|
|
}
|
|
|
|
static void cell_pci_dma_dev_setup(struct pci_dev *dev)
|
|
{
|
|
cell_dma_dev_setup(&dev->dev);
|
|
}
|
|
|
|
static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action,
|
|
void *data)
|
|
{
|
|
struct device *dev = data;
|
|
|
|
/* We are only intereted in device addition */
|
|
if (action != BUS_NOTIFY_ADD_DEVICE)
|
|
return 0;
|
|
|
|
/* We use the PCI DMA ops */
|
|
dev->archdata.dma_ops = get_pci_dma_ops();
|
|
|
|
cell_dma_dev_setup(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct notifier_block cell_of_bus_notifier = {
|
|
.notifier_call = cell_of_bus_notify
|
|
};
|
|
|
|
static int __init cell_iommu_get_window(struct device_node *np,
|
|
unsigned long *base,
|
|
unsigned long *size)
|
|
{
|
|
const void *dma_window;
|
|
unsigned long index;
|
|
|
|
/* Use ibm,dma-window if available, else, hard code ! */
|
|
dma_window = of_get_property(np, "ibm,dma-window", NULL);
|
|
if (dma_window == NULL) {
|
|
*base = 0;
|
|
*size = 0x80000000u;
|
|
return -ENODEV;
|
|
}
|
|
|
|
of_parse_dma_window(np, dma_window, &index, base, size);
|
|
return 0;
|
|
}
|
|
|
|
static void __init cell_iommu_init_one(struct device_node *np, unsigned long offset)
|
|
{
|
|
struct cbe_iommu *iommu;
|
|
unsigned long base, size;
|
|
int nid, i;
|
|
|
|
/* Get node ID */
|
|
nid = of_node_to_nid(np);
|
|
if (nid < 0) {
|
|
printk(KERN_ERR "iommu: failed to get node for %s\n",
|
|
np->full_name);
|
|
return;
|
|
}
|
|
pr_debug("iommu: setting up iommu for node %d (%s)\n",
|
|
nid, np->full_name);
|
|
|
|
/* XXX todo: If we can have multiple windows on the same IOMMU, which
|
|
* isn't the case today, we probably want here to check wether the
|
|
* iommu for that node is already setup.
|
|
* However, there might be issue with getting the size right so let's
|
|
* ignore that for now. We might want to completely get rid of the
|
|
* multiple window support since the cell iommu supports per-page ioids
|
|
*/
|
|
|
|
if (cbe_nr_iommus >= NR_IOMMUS) {
|
|
printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n",
|
|
np->full_name);
|
|
return;
|
|
}
|
|
|
|
/* Init base fields */
|
|
i = cbe_nr_iommus++;
|
|
iommu = &iommus[i];
|
|
iommu->stab = NULL;
|
|
iommu->nid = nid;
|
|
snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i);
|
|
INIT_LIST_HEAD(&iommu->windows);
|
|
|
|
/* Obtain a window for it */
|
|
cell_iommu_get_window(np, &base, &size);
|
|
|
|
pr_debug("\ttranslating window 0x%lx...0x%lx\n",
|
|
base, base + size - 1);
|
|
|
|
/* Initialize the hardware */
|
|
cell_iommu_setup_hardware(iommu, size);
|
|
|
|
/* Setup the iommu_table */
|
|
cell_iommu_setup_window(iommu, np, base, size,
|
|
offset >> IOMMU_PAGE_SHIFT);
|
|
}
|
|
|
|
static void __init cell_disable_iommus(void)
|
|
{
|
|
int node;
|
|
unsigned long base, val;
|
|
void __iomem *xregs, *cregs;
|
|
|
|
/* Make sure IOC translation is disabled on all nodes */
|
|
for_each_online_node(node) {
|
|
if (cell_iommu_find_ioc(node, &base))
|
|
continue;
|
|
xregs = ioremap(base, IOC_Reg_Size);
|
|
if (xregs == NULL)
|
|
continue;
|
|
cregs = xregs + IOC_IOCmd_Offset;
|
|
|
|
pr_debug("iommu: cleaning up iommu on node %d\n", node);
|
|
|
|
out_be64(xregs + IOC_IOST_Origin, 0);
|
|
(void)in_be64(xregs + IOC_IOST_Origin);
|
|
val = in_be64(cregs + IOC_IOCmd_Cfg);
|
|
val &= ~IOC_IOCmd_Cfg_TE;
|
|
out_be64(cregs + IOC_IOCmd_Cfg, val);
|
|
(void)in_be64(cregs + IOC_IOCmd_Cfg);
|
|
|
|
iounmap(xregs);
|
|
}
|
|
}
|
|
|
|
static int __init cell_iommu_init_disabled(void)
|
|
{
|
|
struct device_node *np = NULL;
|
|
unsigned long base = 0, size;
|
|
|
|
/* When no iommu is present, we use direct DMA ops */
|
|
set_pci_dma_ops(&dma_direct_ops);
|
|
|
|
/* First make sure all IOC translation is turned off */
|
|
cell_disable_iommus();
|
|
|
|
/* If we have no Axon, we set up the spider DMA magic offset */
|
|
if (of_find_node_by_name(NULL, "axon") == NULL)
|
|
dma_direct_offset = SPIDER_DMA_OFFSET;
|
|
|
|
/* Now we need to check to see where the memory is mapped
|
|
* in PCI space. We assume that all busses use the same dma
|
|
* window which is always the case so far on Cell, thus we
|
|
* pick up the first pci-internal node we can find and check
|
|
* the DMA window from there.
|
|
*/
|
|
for_each_node_by_name(np, "axon") {
|
|
if (np->parent == NULL || np->parent->parent != NULL)
|
|
continue;
|
|
if (cell_iommu_get_window(np, &base, &size) == 0)
|
|
break;
|
|
}
|
|
if (np == NULL) {
|
|
for_each_node_by_name(np, "pci-internal") {
|
|
if (np->parent == NULL || np->parent->parent != NULL)
|
|
continue;
|
|
if (cell_iommu_get_window(np, &base, &size) == 0)
|
|
break;
|
|
}
|
|
}
|
|
of_node_put(np);
|
|
|
|
/* If we found a DMA window, we check if it's big enough to enclose
|
|
* all of physical memory. If not, we force enable IOMMU
|
|
*/
|
|
if (np && size < lmb_end_of_DRAM()) {
|
|
printk(KERN_WARNING "iommu: force-enabled, dma window"
|
|
" (%ldMB) smaller than total memory (%ldMB)\n",
|
|
size >> 20, lmb_end_of_DRAM() >> 20);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dma_direct_offset += base;
|
|
|
|
printk("iommu: disabled, direct DMA offset is 0x%lx\n",
|
|
dma_direct_offset);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init cell_iommu_init(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
if (!machine_is(cell))
|
|
return -ENODEV;
|
|
|
|
/* If IOMMU is disabled or we have little enough RAM to not need
|
|
* to enable it, we setup a direct mapping.
|
|
*
|
|
* Note: should we make sure we have the IOMMU actually disabled ?
|
|
*/
|
|
if (iommu_is_off ||
|
|
(!iommu_force_on && lmb_end_of_DRAM() <= 0x80000000ull))
|
|
if (cell_iommu_init_disabled() == 0)
|
|
goto bail;
|
|
|
|
/* Setup various ppc_md. callbacks */
|
|
ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup;
|
|
ppc_md.tce_build = tce_build_cell;
|
|
ppc_md.tce_free = tce_free_cell;
|
|
|
|
/* Create an iommu for each /axon node. */
|
|
for_each_node_by_name(np, "axon") {
|
|
if (np->parent == NULL || np->parent->parent != NULL)
|
|
continue;
|
|
cell_iommu_init_one(np, 0);
|
|
}
|
|
|
|
/* Create an iommu for each toplevel /pci-internal node for
|
|
* old hardware/firmware
|
|
*/
|
|
for_each_node_by_name(np, "pci-internal") {
|
|
if (np->parent == NULL || np->parent->parent != NULL)
|
|
continue;
|
|
cell_iommu_init_one(np, SPIDER_DMA_OFFSET);
|
|
}
|
|
|
|
/* Setup default PCI iommu ops */
|
|
set_pci_dma_ops(&dma_iommu_ops);
|
|
|
|
bail:
|
|
/* Register callbacks on OF platform device addition/removal
|
|
* to handle linking them to the right DMA operations
|
|
*/
|
|
bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier);
|
|
|
|
return 0;
|
|
}
|
|
arch_initcall(cell_iommu_init);
|
|
|