2540003686
Update the mapping of the memory controler registers and add the missing definitions of the register block for the SSMC. The register contents definitions can be found in the pl093 header. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
247 lines
5.7 KiB
C
247 lines
5.7 KiB
C
/* linux/arch/arm/mach-s3c2412/s3c2412.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* http://armlinux.simtec.co.uk/.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#include <asm/proc-fns.h>
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#include <asm/irq.h>
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#include <mach/reset.h>
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#include <mach/idle.h>
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#include <plat/cpu-freq.h>
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#include <mach/regs-clock.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-power.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-gpioj.h>
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#include <mach/regs-dsc.h>
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#include <plat/regs-spi.h>
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#include <mach/regs-s3c2412.h>
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#include <plat/s3c2412.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/pm.h>
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#include <plat/pll.h>
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#ifndef CONFIG_CPU_S3C2412_ONLY
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void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
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static inline void s3c2412_init_gpio2(void)
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{
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s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
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}
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#else
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#define s3c2412_init_gpio2() do { } while(0)
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#endif
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/* Initial IO mappings */
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static struct map_desc s3c2412_iodesc[] __initdata = {
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IODESC_ENT(CLKPWR),
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IODESC_ENT(TIMER),
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IODESC_ENT(WATCHDOG),
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{
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.virtual = (unsigned long)S3C2412_VA_SSMC,
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.pfn = __phys_to_pfn(S3C2412_PA_SSMC),
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.length = SZ_1M,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long)S3C2412_VA_EBI,
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.pfn = __phys_to_pfn(S3C2412_PA_EBI),
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.length = SZ_1M,
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.type = MT_DEVICE,
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},
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};
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/* uart registration process */
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void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
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/* rename devices that are s3c2412/s3c2413 specific */
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s3c_device_sdi.name = "s3c2412-sdi";
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s3c_device_lcd.name = "s3c2412-lcd";
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s3c_device_nand.name = "s3c2412-nand";
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/* alter IRQ of SDI controller */
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s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
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s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
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/* spi channel related changes, s3c2412/13 specific */
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s3c_device_spi0.name = "s3c2412-spi";
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s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
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s3c_device_spi1.name = "s3c2412-spi";
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s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
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s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
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}
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/* s3c2412_idle
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*
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* use the standard idle call by ensuring the idle mode
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* in power config, then issuing the idle co-processor
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* instruction
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*/
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static void s3c2412_idle(void)
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{
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unsigned long tmp;
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/* ensure our idle mode is to go to idle */
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tmp = __raw_readl(S3C2412_PWRCFG);
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tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
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tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
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__raw_writel(tmp, S3C2412_PWRCFG);
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cpu_do_idle();
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}
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static void s3c2412_hard_reset(void)
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{
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/* errata "Watch-dog/Software Reset Problem" specifies that
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* this reset must be done with the SYSCLK sourced from
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* EXTCLK instead of FOUT to avoid a glitch in the reset
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* mechanism.
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*
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* See the watchdog section of the S3C2412 manual for more
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* information on this fix.
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*/
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__raw_writel(0x00, S3C2412_CLKSRC);
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__raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
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mdelay(1);
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}
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/* s3c2412_map_io
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*
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* register the standard cpu IO areas, and any passed in from the
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* machine specific initialisation.
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*/
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void __init s3c2412_map_io(void)
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{
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/* move base of IO */
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s3c2412_init_gpio2();
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/* set our idle function */
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s3c24xx_idle = s3c2412_idle;
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/* set custom reset hook */
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s3c24xx_reset_hook = s3c2412_hard_reset;
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/* register our io-tables */
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iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
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}
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void __init_or_cpufreq s3c2412_setup_clocks(void)
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{
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struct clk *xtal_clk;
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unsigned long tmp;
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unsigned long xtal;
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unsigned long fclk;
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unsigned long hclk;
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unsigned long pclk;
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xtal_clk = clk_get(NULL, "xtal");
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xtal = clk_get_rate(xtal_clk);
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clk_put(xtal_clk);
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/* now we've got our machine bits initialised, work out what
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* clocks we've got */
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fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
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clk_mpll.rate = fclk;
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tmp = __raw_readl(S3C2410_CLKDIVN);
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/* work out clock scalings */
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hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
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hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
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pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
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/* print brieft summary of clocks, etc */
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printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
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print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
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s3c24xx_setup_clocks(fclk, hclk, pclk);
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}
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void __init s3c2412_init_clocks(int xtal)
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{
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/* initialise the clocks here, to allow other things like the
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* console to use them
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*/
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s3c24xx_register_baseclocks(xtal);
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s3c2412_setup_clocks();
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s3c2412_baseclk_add();
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}
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/* need to register class before we actually register the device, and
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* we also need to ensure that it has been initialised before any of the
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* drivers even try to use it (even if not on an s3c2412 based system)
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* as a driver which may support both 2410 and 2440 may try and use it.
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*/
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struct sysdev_class s3c2412_sysclass = {
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.name = "s3c2412-core",
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};
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static int __init s3c2412_core_init(void)
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{
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return sysdev_class_register(&s3c2412_sysclass);
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}
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core_initcall(s3c2412_core_init);
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static struct sys_device s3c2412_sysdev = {
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.cls = &s3c2412_sysclass,
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};
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int __init s3c2412_init(void)
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{
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printk("S3C2412: Initialising architecture\n");
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return sysdev_register(&s3c2412_sysdev);
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}
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