a0675c25d6
With everything separated and prepared, we implement a model of a GICv3 distributor and redistributors by using the existing framework to provide handler functions for each register group. Currently we limit the emulation to a model enforcing a single security state, with SRE==1 (forcing system register access) and ARE==1 (allowing more than 8 VCPUs). We share some of the functions provided for GICv2 emulation, but take the different ways of addressing (v)CPUs into account. Save and restore is currently not implemented. Similar to the split-off of the GICv2 specific code, the new emulation code goes into a new file (vgic-v3-emul.c). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
123 lines
4.1 KiB
C
123 lines
4.1 KiB
C
/*
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* Copyright (C) 2012-2014 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from virt/kvm/arm/vgic.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __KVM_VGIC_H__
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#define __KVM_VGIC_H__
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#define VGIC_ADDR_UNDEF (-1)
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#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
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#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
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#define IMPLEMENTER_ARM 0x43b
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#define ACCESS_READ_VALUE (1 << 0)
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#define ACCESS_READ_RAZ (0 << 0)
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#define ACCESS_READ_MASK(x) ((x) & (1 << 0))
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#define ACCESS_WRITE_IGNORED (0 << 1)
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#define ACCESS_WRITE_SETBIT (1 << 1)
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#define ACCESS_WRITE_CLEARBIT (2 << 1)
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#define ACCESS_WRITE_VALUE (3 << 1)
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#define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
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#define VCPU_NOT_ALLOCATED ((u8)-1)
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unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x);
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void vgic_update_state(struct kvm *kvm);
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int vgic_init_common_maps(struct kvm *kvm);
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u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset);
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u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset);
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void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq);
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void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq);
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void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq);
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void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
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int irq, int val);
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void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq);
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void vgic_unqueue_irqs(struct kvm_vcpu *vcpu);
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void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
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phys_addr_t offset, int mode);
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bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
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phys_addr_t offset);
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static inline
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u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
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{
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return le32_to_cpu(*((u32 *)mmio->data)) & mask;
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}
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static inline
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void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
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{
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*((u32 *)mmio->data) = cpu_to_le32(value) & mask;
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}
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struct kvm_mmio_range {
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phys_addr_t base;
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unsigned long len;
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int bits_per_irq;
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bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
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phys_addr_t offset);
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};
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static inline bool is_in_range(phys_addr_t addr, unsigned long len,
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phys_addr_t baseaddr, unsigned long size)
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{
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return (addr >= baseaddr) && (addr + len <= baseaddr + size);
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}
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const
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struct kvm_mmio_range *vgic_find_range(const struct kvm_mmio_range *ranges,
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struct kvm_exit_mmio *mmio,
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phys_addr_t offset);
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bool vgic_handle_mmio_range(struct kvm_vcpu *vcpu, struct kvm_run *run,
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struct kvm_exit_mmio *mmio,
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const struct kvm_mmio_range *ranges,
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unsigned long mmio_base);
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bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
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phys_addr_t offset, int vcpu_id, int access);
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bool vgic_handle_set_pending_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
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phys_addr_t offset, int vcpu_id);
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bool vgic_handle_clear_pending_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
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phys_addr_t offset, int vcpu_id);
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bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio,
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phys_addr_t offset);
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void vgic_kick_vcpus(struct kvm *kvm);
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int vgic_has_attr_regs(const struct kvm_mmio_range *ranges, phys_addr_t offset);
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int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr);
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int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr);
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int vgic_init(struct kvm *kvm);
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void vgic_v2_init_emulation(struct kvm *kvm);
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void vgic_v3_init_emulation(struct kvm *kvm);
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#endif
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