02c981c07b
SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
29 lines
535 B
C
29 lines
535 B
C
/*
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* arch/arm/mach-prima2/include/mach/system.h
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#ifndef __MACH_SYSTEM_H__
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#define __MACH_SYSTEM_H__
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#include <linux/bitops.h>
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#include <mach/hardware.h>
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#define SIRFSOC_SYS_RST_BIT BIT(31)
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extern void __iomem *sirfsoc_rstc_base;
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static inline void arch_idle(void)
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{
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cpu_do_idle();
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}
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static inline void arch_reset(char mode, const char *cmd)
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{
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writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
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}
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#endif
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