d4e1c889c1
This patchs allows the offset to the first page of physical memory to be on any 2MB boundary whereas the previous code could only handle psysical offset to any 16MB boundary (0xNN000000) or any 1MB boundary below 0x01000000 (e.g. 0x00N00000). The problem is a consequence of the orr one-byte syntax, so we fix this and we can place the first bank of memory at 0x28e00000. I have also included an explicit check that disallow compilation when PHYS_OFFSET is not on a 2MiB boundary. head.S would be the proper place to have this at since this is the first file that attempts to use PHYS_OFFSET during compile. Signed-off-by: Linus Walleij <triad@df.lth.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
322 lines
8.6 KiB
ArmAsm
322 lines
8.6 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Kernel startup code for all 32-bit CPUs
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/domain.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/system.h>
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#if (PHYS_OFFSET & 0x001fffff)
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#error "PHYS_OFFSET must be at an even 2MiB boundary!"
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#endif
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#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
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#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
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/*
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* swapper_pg_dir is the virtual address of the initial page table.
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* We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
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* make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
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* the least significant 16 bits to be 0x8000, but we could probably
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* relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
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*/
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#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
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#error KERNEL_RAM_VADDR must start at 0xXXXX8000
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
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.macro pgtbl, rd
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ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
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.endm
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#ifdef CONFIG_XIP_KERNEL
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#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
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#else
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#define TEXTADDR KERNEL_RAM_VADDR
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* This is normally called from the decompressor code. The requirements
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* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
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* r1 = machine nr.
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*
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* This code is mostly position independent, so if you link the kernel at
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* 0xc0008000, you call this at __pa(0xc0008000).
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*
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* See linux/arch/arm/tools/mach-types for the complete list of machine
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* numbers for r1.
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*
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* We're trying to keep crap to a minimum; DO NOT add any machine specific
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* crap here - that's what the boot loader (or in extreme, well justified
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* circumstances, zImage) is for.
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*/
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__INIT
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.type stext, %function
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ENTRY(stext)
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
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@ and irqs disabled
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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beq __error_p @ yes, error 'p'
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bl __lookup_machine_type @ r5=machinfo
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movs r8, r5 @ invalid machine (r5=0)?
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beq __error_a @ yes, error 'a'
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bl __create_page_tables
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/*
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* The following calls CPU specific code in a position independent
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* manner. See arch/arm/mm/proc-*.S for details. r10 = base of
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* xxx_proc_info structure selected by __lookup_machine_type
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* above. On return, the CPU will be ready for the MMU to be
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* turned on, and r0 will hold the CPU control register value.
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*/
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ldr r13, __switch_data @ address to jump to after
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@ mmu has been enabled
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adr lr, __enable_mmu @ return (PIC) address
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add pc, r10, #PROCINFO_INITFUNC
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#if defined(CONFIG_SMP)
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.type secondary_startup, #function
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*
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* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
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* the processor type - there is no need to check the machine type
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* as it has already been validated by the primary processor.
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*/
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type
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movs r10, r5 @ invalid processor?
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moveq r0, #'p' @ yes, error 'p'
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beq __error
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/*
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* Use the page tables supplied from __cpu_up.
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*/
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adr r4, __secondary_data
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ldmia r4, {r5, r7, r13} @ address to jump to after
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sub r4, r4, r5 @ mmu has been enabled
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ldr r4, [r7, r4] @ get secondary_data.pgdir
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adr lr, __enable_mmu @ return address
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add pc, r10, #PROCINFO_INITFUNC @ initialise processor
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@ (return control reg)
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/*
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* r6 = &secondary_data
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*/
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ENTRY(__secondary_switched)
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ldr sp, [r7, #4] @ get secondary_data.stack
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mov fp, #0
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b secondary_start_kernel
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.type __secondary_data, %object
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__secondary_data:
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.long .
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.long secondary_data
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.long __secondary_switched
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#endif /* defined(CONFIG_SMP) */
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/*
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* Setup common bits before finally enabling the MMU. Essentially
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* this is just loading the page table pointer and domain access
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* registers.
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*/
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.type __enable_mmu, %function
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__enable_mmu:
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#ifdef CONFIG_ALIGNMENT_TRAP
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orr r0, r0, #CR_A
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#else
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bic r0, r0, #CR_A
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#endif
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CR_C
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#endif
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#ifdef CONFIG_CPU_BPREDICT_DISABLE
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bic r0, r0, #CR_Z
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #CR_I
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#endif
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mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_IO, DOMAIN_CLIENT))
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mcr p15, 0, r5, c3, c0, 0 @ load domain access register
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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b __turn_mmu_on
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/*
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* Enable the MMU. This completely changes the structure of the visible
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* memory space. You will not be able to trace execution through this.
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* If you have an enquiry about this, *please* check the linux-arm-kernel
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* mailing list archives BEFORE sending another post to the list.
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*
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* r0 = cp#15 control register
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* r13 = *virtual* address to jump to upon completion
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*
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* other registers depend on the function called upon completion
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*/
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.align 5
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.type __turn_mmu_on, %function
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__turn_mmu_on:
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mov r0, r0
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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mrc p15, 0, r3, c0, c0, 0 @ read id reg
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mov r3, r3
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mov r3, r3
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mov pc, r13
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/*
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* Setup the initial page tables. We only setup the barest
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* amount which are required to get the kernel running, which
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* generally means mapping in the kernel code.
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*
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* r8 = machinfo
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* r9 = cpuid
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* r10 = procinfo
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*
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* Returns:
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* r0, r3, r6, r7 corrupted
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* r4 = physical page table address
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*/
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.type __create_page_tables, %function
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__create_page_tables:
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pgtbl r4 @ page table address
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/*
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* Clear the 16K level 1 swapper page table
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*/
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mov r0, r4
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mov r3, #0
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add r6, r0, #0x4000
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1: str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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teq r0, r6
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bne 1b
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ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
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/*
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* Create identity mapping for first MB of kernel to
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* cater for the MMU enable. This identity mapping
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* will be removed by paging_init(). We use our current program
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* counter to determine corresponding section base address.
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*/
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mov r6, pc, lsr #20 @ start of kernel section
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orr r3, r7, r6, lsl #20 @ flags + kernel base
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str r3, [r4, r6, lsl #2] @ identity mapping
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/*
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* Now setup the pagetables for our kernel direct
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* mapped region.
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*/
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add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
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str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
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ldr r6, =(_end - PAGE_OFFSET - 1) @ r6 = number of sections
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mov r6, r6, lsr #20 @ needed for kernel minus 1
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1: add r3, r3, #1 << 20
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str r3, [r0, #4]!
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subs r6, r6, #1
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bgt 1b
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/*
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* Then map first 1MB of ram in case it contains our boot params.
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*/
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add r0, r4, #PAGE_OFFSET >> 18
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orr r6, r7, #(PHYS_OFFSET & 0xff000000)
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orr r6, r6, #(PHYS_OFFSET & 0x00e00000)
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str r6, [r0]
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#ifdef CONFIG_XIP_KERNEL
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/*
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* Map some ram to cover our .data and .bss areas.
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* Mapping 3MB should be plenty.
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*/
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sub r3, r4, #PHYS_OFFSET
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mov r3, r3, lsr #20
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add r0, r0, r3, lsl #2
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add r6, r6, r3, lsl #20
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str r6, [r0], #4
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add r6, r6, #(1 << 20)
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str r6, [r0], #4
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add r6, r6, #(1 << 20)
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str r6, [r0]
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#endif
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#ifdef CONFIG_DEBUG_LL
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ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
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/*
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* Map in IO space for serial debugging.
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* This allows debug messages to be output
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* via a serial console before paging_init.
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*/
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ldr r3, [r8, #MACHINFO_PGOFFIO]
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add r0, r4, r3
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rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
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cmp r3, #0x0800 @ limit to 512MB
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movhi r3, #0x0800
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add r6, r0, r3
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ldr r3, [r8, #MACHINFO_PHYSIO]
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orr r3, r3, r7
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1: str r3, [r0], #4
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add r3, r3, #1 << 20
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teq r0, r6
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bne 1b
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#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
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/*
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* If we're using the NetWinder or CATS, we also need to map
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* in the 16550-type serial port for the debug messages
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*/
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add r0, r4, #0xff000000 >> 18
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orr r3, r7, #0x7c000000
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str r3, [r0]
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#endif
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#ifdef CONFIG_ARCH_RPC
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/*
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* Map in screen at 0x02000000 & SCREEN2_BASE
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* Similar reasons here - for debug. This is
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* only for Acorn RiscPC architectures.
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*/
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add r0, r4, #0x02000000 >> 18
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orr r3, r7, #0x02000000
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str r3, [r0]
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add r0, r4, #0xd8000000 >> 18
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str r3, [r0]
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#endif
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#endif
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mov pc, lr
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.ltorg
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#include "head-common.S"
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