9e33ce79f8
PETXCFG is defined at 0xFF03, the old 0xFE49 not used any more. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
355 lines
10 KiB
C
355 lines
10 KiB
C
/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* Wei WANG <wei_wang@realsil.com.cn>
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mfd/rtsx_pci.h>
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#include "rtsx_pcr.h"
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static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
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{
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u8 val;
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rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
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return val & 0x0F;
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}
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static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
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{
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u8 driving_3v3[4][3] = {
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{0x11, 0x11, 0x11},
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{0x55, 0x55, 0x5C},
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{0x99, 0x99, 0x92},
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{0x99, 0x99, 0x92},
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};
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u8 driving_1v8[4][3] = {
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{0x3C, 0x3C, 0x3C},
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{0xB3, 0xB3, 0xB3},
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{0xFE, 0xFE, 0xFE},
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{0xC4, 0xC4, 0xC4},
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};
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u8 (*driving)[3], drive_sel;
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if (voltage == OUTPUT_3V3) {
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driving = driving_3v3;
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drive_sel = pcr->sd30_drive_sel_3v3;
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} else {
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driving = driving_1v8;
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drive_sel = pcr->sd30_drive_sel_1v8;
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}
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
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0xFF, driving[drive_sel][0]);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
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0xFF, driving[drive_sel][1]);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
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0xFF, driving[drive_sel][2]);
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}
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static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
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{
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u32 reg;
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
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dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
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if (!rtsx_vendor_setting_valid(reg))
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return;
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pcr->aspm_en = rtsx_reg_to_aspm(reg);
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pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
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pcr->card_drive_sel &= 0x3F;
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pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
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dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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if (rtsx_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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}
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static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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/* Set relink_time to 0 */
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
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if (pm_state == HOST_ENTER_S3)
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rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
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rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
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}
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static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rtsx_pci_init_cmd(pcr);
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/* Configure GPIO as output */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
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/* Reset ASPM state to default value */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
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/* Switch LDO3318 source from DV33 to card_3v3 */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
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/* LED shine disabled, set initial shine cycle period */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
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/* Configure driving */
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rts5249_fill_driving(pcr, OUTPUT_3V3);
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
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{
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int err;
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err = rtsx_gops_pm_reset(pcr);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV,
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PHY_REG_REV_RESV | PHY_REG_REV_RXIDLE_LATCHED |
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PHY_REG_REV_P1_EN | PHY_REG_REV_RXIDLE_EN |
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PHY_REG_REV_RX_PWST | PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 |
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PHY_REG_REV_STOP_CLKRD | PHY_REG_REV_STOP_CLKWR);
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if (err < 0)
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return err;
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msleep(1);
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err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
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PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
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PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
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PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
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PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
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PHY_PCR_RSSI_EN);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
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PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
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PHY_RCR2_CDR_CP_10 | PHY_RCR2_CDR_SR_2 |
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PHY_RCR2_FREQSEL_12 | PHY_RCR2_CPADJEN |
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PHY_RCR2_CDR_SC_8 | PHY_RCR2_CALIB_LATE);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
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PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
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PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
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PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
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PHY_FLD4_BER_CHK_EN);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_RDR, PHY_RDR_RXDSEL_1_9);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
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PHY_RCR1_ADP_TIME | PHY_RCR1_VCO_COARSE);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
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PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
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PHY_FLD3_RXDELINK);
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if (err < 0)
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return err;
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return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
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PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
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PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
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PHY_TUNE_TUNED12);
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}
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static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
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}
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static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
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}
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static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
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}
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static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
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}
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static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
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{
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int err;
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x02);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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msleep(5);
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_VCC_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x06);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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return 0;
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}
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static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
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{
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_POWER_OFF);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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int err;
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if (voltage == OUTPUT_3V3) {
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err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
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if (err < 0)
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return err;
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} else if (voltage == OUTPUT_1V8) {
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err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
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if (err < 0)
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return err;
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} else {
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return -EINVAL;
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}
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/* set pad drive */
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rtsx_pci_init_cmd(pcr);
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rts5249_fill_driving(pcr, voltage);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static const struct pcr_ops rts5249_pcr_ops = {
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.fetch_vendor_settings = rts5249_fetch_vendor_settings,
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.extra_init_hw = rts5249_extra_init_hw,
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.optimize_phy = rts5249_optimize_phy,
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.turn_on_led = rts5249_turn_on_led,
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.turn_off_led = rts5249_turn_off_led,
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.enable_auto_blink = rts5249_enable_auto_blink,
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.disable_auto_blink = rts5249_disable_auto_blink,
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.card_power_on = rts5249_card_power_on,
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.card_power_off = rts5249_card_power_off,
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.switch_output_voltage = rts5249_switch_output_voltage,
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.force_power_down = rts5249_force_power_down,
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};
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/* SD Pull Control Enable:
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* SD_DAT[3:0] ==> pull up
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* SD_CD ==> pull up
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* SD_WP ==> pull up
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* SD_CMD ==> pull up
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* SD_CLK ==> pull down
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*/
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static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
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0,
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};
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/* SD Pull Control Disable:
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* SD_DAT[3:0] ==> pull down
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* SD_CD ==> pull up
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* SD_WP ==> pull down
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* SD_CMD ==> pull down
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* SD_CLK ==> pull down
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*/
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static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
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0,
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};
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/* MS Pull Control Enable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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/* MS Pull Control Disable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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void rts5249_init_params(struct rtsx_pcr *pcr)
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{
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pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
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pcr->num_slots = 2;
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pcr->ops = &rts5249_pcr_ops;
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pcr->flags = 0;
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pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
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pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
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pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
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pcr->aspm_en = ASPM_L1_EN;
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pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
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pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
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pcr->ic_version = rts5249_get_ic_version(pcr);
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pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
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pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
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pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
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pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
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}
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