9d4436a6fb
This implements initial support for the SH7206 (SH-2A) and SH7619 (SH-2) MMU-less CPUs. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
163 lines
5.2 KiB
C
163 lines
5.2 KiB
C
/*
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* Interrupt handling for IPR-based IRQ.
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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* Copyright (C) 2006 Paul Mundt
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*
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* Supported system:
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* On-chip supporting modules (TMU, RTC, etc.).
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* On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
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* Hitachi SolutionEngine external I/O:
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* MS7709SE01, MS7709ASE01, and MS7750SE01
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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static void disable_ipr_irq(unsigned int irq)
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{
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struct ipr_data *p = get_irq_chip_data(irq);
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int shift = p->shift*4;
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/* Set the priority in IPR to 0 */
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ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr);
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}
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static void enable_ipr_irq(unsigned int irq)
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{
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struct ipr_data *p = get_irq_chip_data(irq);
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int shift = p->shift*4;
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/* Set priority in IPR back to original value */
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ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr);
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}
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static struct irq_chip ipr_irq_chip = {
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.name = "IPR",
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.mask = disable_ipr_irq,
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.unmask = enable_ipr_irq,
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.mask_ack = disable_ipr_irq,
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};
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void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs)
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{
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int i;
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for (i = 0; i < nr_irqs; i++) {
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unsigned int irq = table[i].irq;
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disable_irq_nosync(irq);
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set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
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handle_level_irq, "level");
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set_irq_chip_data(irq, &table[i]);
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enable_ipr_irq(irq);
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}
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}
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EXPORT_SYMBOL(make_ipr_irq);
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/*
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* XXX: Move this garbage in to the drivers, and kill off the ridiculous CPU
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* subtype checks.
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*/
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static struct ipr_data sys_ipr_map[] = {
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#ifndef CONFIG_CPU_SUBTYPE_SH7780
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{ TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY },
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{ TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY },
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#ifdef RTC_IRQ
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{ RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY },
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#endif
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#ifdef SCI_ERI_IRQ
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{ SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
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{ SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
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{ SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
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#endif
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#ifdef SCIF1_ERI_IRQ
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{ SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
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{ SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
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{ SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
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{ SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
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#endif
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#ifdef SCIF2_ERI_IRQ
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{ SCIF2_ERI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
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{ SCIF2_RXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
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{ SCIF2_BRI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
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{ SCIF2_TXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
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#endif
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#ifdef SCIF3_ERI_IRQ
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{ SCIF3_ERI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
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{ SCIF3_RXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
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{ SCIF3_BRI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
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{ SCIF3_TXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7300)
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{ SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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#endif
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#ifdef SCIF_ERI_IRQ
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{ SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
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{ SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
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{ SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
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{ SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
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#endif
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#ifdef IRDA_ERI_IRQ
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{ IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
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{ IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
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{ IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
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{ IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
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/*
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* Initialize the Interrupt Controller (INTC)
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* registers to their power on values
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*/
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/*
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* Enable external irq (INTC IRQ mode).
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* You should set corresponding bits of PFC to "00"
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* to enable these interrupts.
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*/
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{ IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY },
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{ IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
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{ IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
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{ IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY },
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{ IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY },
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{ IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY },
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#endif
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#endif
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};
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void __init init_IRQ(void)
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{
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make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map));
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#ifdef CONFIG_CPU_HAS_PINT_IRQ
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init_IRQ_pint();
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#endif
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#ifdef CONFIG_CPU_HAS_INTC2_IRQ
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init_IRQ_intc2();
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#endif
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/* Perform the machine specific initialisation */
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if (sh_mv.mv_init_irq != NULL)
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sh_mv.mv_init_irq();
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irq_ctx_init(smp_processor_id());
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}
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#if !defined(CONFIG_CPU_HAS_PINT_IRQ)
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int ipr_irq_demux(int irq)
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{
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return irq;
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}
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#endif
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