Leonid Yegoshin 26ab96dfa9 MIPS: Add support for interAptiv cores ... The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6163/		2014-01-22 20:19:01 +01:00
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backtrace.c
common.c	MIPS: Add support for interAptiv cores	2014-01-22 20:19:01 +01:00
Makefile	Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into mips-for-linux-next	2012-12-13 19:40:13 +01:00
op_impl.h
op_model_loongson2.c	MIPS: Whitespace cleanup.	2013-02-01 10:00:22 +01:00
op_model_mipsxx.c	MIPS: Add support for interAptiv cores	2014-01-22 20:19:01 +01:00