2ddf3a7922
Replace the simple GPIO chip registration by a platform driver and make ath79_gpio_init() just register the device. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
279 lines
6.5 KiB
C
279 lines
6.5 KiB
C
/*
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* Atheros AR71XX/AR724X/AR913X GPIO API support
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/gpio.h>
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#include <linux/platform_data/gpio-ath79.h>
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#include <linux/of_device.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include "common.h"
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static void __iomem *ath79_gpio_base;
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static u32 ath79_gpio_count;
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static DEFINE_SPINLOCK(ath79_gpio_lock);
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static void __ath79_gpio_set_value(unsigned gpio, int value)
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{
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void __iomem *base = ath79_gpio_base;
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if (value)
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__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);
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}
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static int __ath79_gpio_get_value(unsigned gpio)
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{
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return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
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}
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static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset)
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{
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return __ath79_gpio_get_value(offset);
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}
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static void ath79_gpio_set_value(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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__ath79_gpio_set_value(offset, value);
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}
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static int ath79_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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void __iomem *base = ath79_gpio_base;
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
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base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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return 0;
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}
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static int ath79_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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void __iomem *base = ath79_gpio_base;
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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if (value)
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
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base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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return 0;
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}
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static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *base = ath79_gpio_base;
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
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base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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return 0;
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}
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static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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void __iomem *base = ath79_gpio_base;
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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if (value)
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
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base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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return 0;
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}
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static struct gpio_chip ath79_gpio_chip = {
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.label = "ath79",
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.get = ath79_gpio_get_value,
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.set = ath79_gpio_set_value,
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.direction_input = ath79_gpio_direction_input,
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.direction_output = ath79_gpio_direction_output,
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.base = 0,
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};
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static void __iomem *ath79_gpio_get_function_reg(void)
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{
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u32 reg = 0;
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if (soc_is_ar71xx() ||
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soc_is_ar724x() ||
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soc_is_ar913x() ||
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soc_is_ar933x())
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reg = AR71XX_GPIO_REG_FUNC;
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else if (soc_is_ar934x())
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reg = AR934X_GPIO_REG_FUNC;
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else
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BUG();
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return ath79_gpio_base + reg;
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}
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void ath79_gpio_function_setup(u32 set, u32 clear)
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{
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void __iomem *reg = ath79_gpio_get_function_reg();
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
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/* flush write */
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__raw_readl(reg);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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}
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void ath79_gpio_function_enable(u32 mask)
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{
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ath79_gpio_function_setup(mask, 0);
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}
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void ath79_gpio_function_disable(u32 mask)
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{
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ath79_gpio_function_setup(0, mask);
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}
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static const struct of_device_id ath79_gpio_of_match[] = {
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{ .compatible = "qca,ar7100-gpio" },
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{ .compatible = "qca,ar9340-gpio" },
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{},
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};
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static int ath79_gpio_probe(struct platform_device *pdev)
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{
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struct ath79_gpio_platform_data *pdata = pdev->dev.platform_data;
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struct device_node *np = pdev->dev.of_node;
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struct resource *res;
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bool oe_inverted;
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int err;
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if (np) {
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err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
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if (err) {
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dev_err(&pdev->dev, "ngpios property is not valid\n");
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return err;
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}
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if (ath79_gpio_count >= 32) {
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dev_err(&pdev->dev, "ngpios must be less than 32\n");
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return -EINVAL;
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}
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oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
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} else if (pdata) {
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ath79_gpio_count = pdata->ngpios;
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oe_inverted = pdata->oe_inverted;
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} else {
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dev_err(&pdev->dev, "No DT node or platform data found\n");
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return -EINVAL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ath79_gpio_base = devm_ioremap_nocache(
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&pdev->dev, res->start, resource_size(res));
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if (!ath79_gpio_base)
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return -ENOMEM;
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ath79_gpio_chip.dev = &pdev->dev;
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ath79_gpio_chip.ngpio = ath79_gpio_count;
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if (oe_inverted) {
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ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
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ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
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}
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err = gpiochip_add(&ath79_gpio_chip);
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if (err) {
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dev_err(&pdev->dev,
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"cannot add AR71xx GPIO chip, error=%d", err);
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return err;
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}
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return 0;
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}
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static struct platform_driver ath79_gpio_driver = {
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.driver = {
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.name = "ath79-gpio",
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.of_match_table = ath79_gpio_of_match,
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},
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.probe = ath79_gpio_probe,
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};
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module_platform_driver(ath79_gpio_driver);
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int gpio_get_value(unsigned gpio)
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{
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if (gpio < ath79_gpio_count)
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return __ath79_gpio_get_value(gpio);
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return __gpio_get_value(gpio);
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}
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EXPORT_SYMBOL(gpio_get_value);
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void gpio_set_value(unsigned gpio, int value)
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{
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if (gpio < ath79_gpio_count)
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__ath79_gpio_set_value(gpio, value);
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else
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__gpio_set_value(gpio, value);
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}
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EXPORT_SYMBOL(gpio_set_value);
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int gpio_to_irq(unsigned gpio)
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{
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/* FIXME */
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return -EINVAL;
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}
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EXPORT_SYMBOL(gpio_to_irq);
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int irq_to_gpio(unsigned irq)
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{
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/* FIXME */
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return -EINVAL;
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}
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EXPORT_SYMBOL(irq_to_gpio);
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