8a67f0ef2b
big LITTLE is ARM's new Architecture focussing power/performance needs of modern world. More information about big LITTLE can be found here: http://www.arm.com/products/processors/technologies/biglittleprocessing.php http://lwn.net/Articles/481055/ In order to keep cpufreq support for all big LITTLE platforms simple/generic, this patch tries to add a generic cpufreq driver layer for all big LITTLE platforms. The driver is divided into two parts: - Core driver: Generic and shared across all big LITTLE SoC's - Glue drivers: Per platform drivers providing ops to the core driver This patch adds in a generic glue driver which would extract information from Device Tree. Future SoC's can either reuse the DT glue or write their own depending on the need. Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
65 lines
1.4 KiB
Text
65 lines
1.4 KiB
Text
Generic ARM big LITTLE cpufreq driver's DT glue
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-----------------------------------------------
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This is DT specific glue layer for generic cpufreq driver for big LITTLE
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systems.
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Both required and optional properties listed below must be defined
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under node /cpus/cpu@x. Where x is the first cpu inside a cluster.
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FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster
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must be present contiguously. Generic DT driver will check only node 'x' for
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cpu:x.
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Required properties:
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- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
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for details
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Optional properties:
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- clock-latency: Specify the possible maximum transition latency for clock,
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in unit of nanoseconds.
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Examples:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a15";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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792000 1100000
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396000 950000
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198000 850000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@100 {
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compatible = "arm,cortex-a7";
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reg = <100>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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792000 950000
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396000 750000
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198000 450000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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};
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cpu@101 {
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compatible = "arm,cortex-a7";
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reg = <101>;
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next-level-cache = <&L2>;
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};
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};
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