7230c56441
The current implementation of lazy interrupts handling has some issues that this tries to address. We don't do the various workarounds we need to do when re-enabling interrupts in some cases such as when returning from an interrupt and thus we may still lose or get delayed decrementer or doorbell interrupts. The current scheme also makes it much harder to handle the external "edge" interrupts provided by some BookE processors when using the EPR facility (External Proxy) and the Freescale Hypervisor. Additionally, we tend to keep interrupts hard disabled in a number of cases, such as decrementer interrupts, external interrupts, or when a masked decrementer interrupt is pending. This is sub-optimal. This is an attempt at fixing it all in one go by reworking the way we do the lazy interrupt disabling from the ground up. The base idea is to replace the "hard_enabled" field with a "irq_happened" field in which we store a bit mask of what interrupt occurred while soft-disabled. When re-enabling, either via arch_local_irq_restore() or when returning from an interrupt, we can now decide what to do by testing bits in that field. We then implement replaying of the missed interrupts either by re-using the existing exception frame (in exception exit case) or via the creation of a new one from an assembly trampoline (in the arch_local_irq_enable case). This removes the need to play with the decrementer to try to create fake interrupts, among others. In addition, this adds a few refinements: - We no longer hard disable decrementer interrupts that occur while soft-disabled. We now simply bump the decrementer back to max (on BookS) or leave it stopped (on BookE) and continue with hard interrupts enabled, which means that we'll potentially get better sample quality from performance monitor interrupts. - Timer, decrementer and doorbell interrupts now hard-enable shortly after removing the source of the interrupt, which means they no longer run entirely hard disabled. Again, this will improve perf sample quality. - On Book3E 64-bit, we now make the performance monitor interrupt act as an NMI like Book3S (the necessary C code for that to work appear to already be present in the FSL perf code, notably calling nmi_enter instead of irq_enter). (This also fixes a bug where BookE perfmon interrupts could clobber r14 ... oops) - We could make "masked" decrementer interrupts act as NMIs when doing timer-based perf sampling to improve the sample quality. Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- v2: - Add hard-enable to decrementer, timer and doorbells - Fix CR clobber in masked irq handling on BookE - Make embedded perf interrupt act as an NMI - Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want to retrigger an interrupt without preventing hard-enable v3: - Fix or vs. ori bug on Book3E - Fix enabling of interrupts for some exceptions on Book3E v4: - Fix resend of doorbells on return from interrupt on Book3E v5: - Rebased on top of my latest series, which involves some significant rework of some aspects of the patch. v6: - 32-bit compile fix - more compile fixes with various .config combos - factor out the asm code to soft-disable interrupts - remove the C wrapper around preempt_schedule_irq v7: - Fix a bug with hard irq state tracking on native power7
198 lines
4.1 KiB
C
198 lines
4.1 KiB
C
/*
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* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
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*/
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#ifndef _ASM_POWERPC_HW_IRQ_H
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#define _ASM_POWERPC_HW_IRQ_H
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#ifdef __KERNEL__
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#include <linux/errno.h>
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#include <linux/compiler.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#ifdef CONFIG_PPC64
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/*
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* PACA flags in paca->irq_happened.
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*
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* This bits are set when interrupts occur while soft-disabled
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* and allow a proper replay. Additionally, PACA_IRQ_HARD_DIS
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* is set whenever we manually hard disable.
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*/
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#define PACA_IRQ_HARD_DIS 0x01
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#define PACA_IRQ_DBELL 0x02
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#define PACA_IRQ_EE 0x04
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#define PACA_IRQ_DEC 0x08 /* Or FIT */
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#define PACA_IRQ_EE_EDGE 0x10 /* BookE only */
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#endif /* CONFIG_PPC64 */
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#ifndef __ASSEMBLY__
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extern void __replay_interrupt(unsigned int vector);
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extern void timer_interrupt(struct pt_regs *);
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#ifdef CONFIG_PPC64
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#include <asm/paca.h>
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static inline unsigned long arch_local_save_flags(void)
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{
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unsigned long flags;
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asm volatile(
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"lbz %0,%1(13)"
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: "=r" (flags)
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: "i" (offsetof(struct paca_struct, soft_enabled)));
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return flags;
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}
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static inline unsigned long arch_local_irq_disable(void)
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{
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unsigned long flags, zero;
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asm volatile(
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"li %1,0; lbz %0,%2(13); stb %1,%2(13)"
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: "=r" (flags), "=&r" (zero)
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: "i" (offsetof(struct paca_struct, soft_enabled))
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: "memory");
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return flags;
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}
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extern void arch_local_irq_restore(unsigned long);
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static inline void arch_local_irq_enable(void)
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{
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arch_local_irq_restore(1);
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}
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static inline unsigned long arch_local_irq_save(void)
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{
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return arch_local_irq_disable();
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}
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static inline bool arch_irqs_disabled_flags(unsigned long flags)
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{
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return flags == 0;
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}
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static inline bool arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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#ifdef CONFIG_PPC_BOOK3E
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#define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory");
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#define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory");
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#else
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#define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr | MSR_EE, 1)
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#define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1)
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#endif
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static inline void hard_irq_disable(void)
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{
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__hard_irq_disable();
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get_paca()->soft_enabled = 0;
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get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
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}
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/*
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* This is called by asynchronous interrupts to conditionally
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* re-enable hard interrupts when soft-disabled after having
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* cleared the source of the interrupt
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*/
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static inline void may_hard_irq_enable(void)
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{
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get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS;
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if (!(get_paca()->irq_happened & PACA_IRQ_EE))
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__hard_irq_enable();
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}
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static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
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{
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return !regs->softe;
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}
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#else /* CONFIG_PPC64 */
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#define SET_MSR_EE(x) mtmsr(x)
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static inline unsigned long arch_local_save_flags(void)
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{
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return mfmsr();
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}
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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#if defined(CONFIG_BOOKE)
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asm volatile("wrtee %0" : : "r" (flags) : "memory");
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#else
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mtmsr(flags);
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#endif
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}
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static inline unsigned long arch_local_irq_save(void)
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{
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unsigned long flags = arch_local_save_flags();
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#ifdef CONFIG_BOOKE
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asm volatile("wrteei 0" : : : "memory");
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#else
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SET_MSR_EE(flags & ~MSR_EE);
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#endif
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return flags;
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}
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static inline void arch_local_irq_disable(void)
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{
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#ifdef CONFIG_BOOKE
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asm volatile("wrteei 0" : : : "memory");
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#else
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arch_local_irq_save();
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#endif
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}
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static inline void arch_local_irq_enable(void)
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{
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#ifdef CONFIG_BOOKE
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asm volatile("wrteei 1" : : : "memory");
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#else
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unsigned long msr = mfmsr();
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SET_MSR_EE(msr | MSR_EE);
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#endif
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}
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static inline bool arch_irqs_disabled_flags(unsigned long flags)
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{
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return (flags & MSR_EE) == 0;
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}
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static inline bool arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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#define hard_irq_disable() arch_local_irq_disable()
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static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
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{
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return !(regs->msr & MSR_EE);
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}
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static inline void may_hard_irq_enable(void) { }
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#endif /* CONFIG_PPC64 */
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#define ARCH_IRQ_INIT_FLAGS IRQ_NOREQUEST
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/*
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* interrupt-retrigger: should we handle this via lost interrupts and IPIs
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* or should we not care like we do now ? --BenH.
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*/
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struct irq_chip;
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_HW_IRQ_H */
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