9adf5d222c
Samsung S5P SoCs have the same interrupt type defines for both external interrupts and gpio interrupts. This patch removes all duplicates from S5PC100 and S5PV210 specific includes as well as gpio interrupt code and put a common defines to plat/irqs.h NOTE: Do not use this for S5P6440 and S5P6450. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: add note for S5P64X0] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
75 lines
2.9 KiB
C
75 lines
2.9 KiB
C
/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
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*
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* Copyright 2009 Samsung Electronics Co.
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* Byungho Min <bhmin@samsung.com>
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*
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* S5PC100 - GPIO register definitions
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*/
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#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
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#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
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#include <mach/map.h>
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/* S5PC100 */
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#define S5PC100_GPIO_BASE S5P_VA_GPIO
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#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
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#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
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#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
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#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060)
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#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080)
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#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0)
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#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0)
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#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0)
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#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100)
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#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120)
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#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140)
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#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160)
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#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180)
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#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0)
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#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0)
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#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00)
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#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20)
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#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40)
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#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60)
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#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0)
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#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200)
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#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220)
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#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240)
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#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260)
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#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280)
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#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0)
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#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0)
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#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0)
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#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300)
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#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320)
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#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340)
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#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
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#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
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#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
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#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
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#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
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#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
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#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4))
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#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00)
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#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4))
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#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40)
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#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4))
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#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
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#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
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#define EINT_MODE S3C_GPIO_SFN(0x2)
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#define EINT_GPIO_0(x) S5PC100_GPH0(x)
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#define EINT_GPIO_1(x) S5PC100_GPH1(x)
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#define EINT_GPIO_2(x) S5PC100_GPH2(x)
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#define EINT_GPIO_3(x) S5PC100_GPH3(x)
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#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
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