2ef9481e66
This patch removes all self references and fixes references to files in the now defunct arch/ppc64 tree. I think this accomplises everything wanted, though there might be a few references I missed. Signed-off-by: Jon Mason <jdmason@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
78 lines
2.4 KiB
C
78 lines
2.4 KiB
C
/*
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* Definitions for Motorola SPS Sandpoint Test Platform
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* 2000-2003 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* Sandpoint uses the CHRP map (Map B).
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*/
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#ifndef __PPC_PLATFORMS_SANDPOINT_H
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#define __PPC_PLATFORMS_SANDPOINT_H
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#include <asm/ppcboot.h>
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#if 0
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/* The Sandpoint X3 allows the IDE interrupt to be directly connected
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* from the Windbond (PCI INTC or INTD) to the serial EPIC. Someday
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* we should try this, but it was easier to use the existing 83c553
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* initialization than change it to route the different interrupts :-).
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* -- Dan
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*/
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#define SANDPOINT_IDE_INT0 23 /* EPIC 7 */
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#define SANDPOINT_IDE_INT1 24 /* EPIC 8 */
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#else
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#define SANDPOINT_IDE_INT0 14 /* 8259 Test */
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#define SANDPOINT_IDE_INT1 15 /* 8259 Test */
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#endif
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/*
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* The sandpoint boards have processor modules that either have an 8240 or
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* an MPC107 host bridge on them. These bridges have an IDSEL line that allows
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* them to respond to PCI transactions as if they were a normal PCI devices.
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* However, the processor on the processor side of the bridge can not reach
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* out onto the PCI bus and then select the bridge or bad things will happen
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* (documented in the 8240 and 107 manuals).
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* Because of this, we always skip the bridge PCI device when accessing the
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* PCI bus. The PCI slot that the bridge occupies is defined by the macro
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* below.
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*/
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#define SANDPOINT_HOST_BRIDGE_IDSEL 12
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/*
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* Serial defines.
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*/
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#define SANDPOINT_SERIAL_0 0xfe0003f8
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#define SANDPOINT_SERIAL_1 0xfe0002f8
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#define RS_TABLE_SIZE 2
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/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
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#define BASE_BAUD ( 1843200 / 16 )
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#define UART_CLK 1843200
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#ifdef CONFIG_SERIAL_DETECT_IRQ
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
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#else
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF)
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#endif
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#define STD_SERIAL_PORT_DFNS \
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{ 0, BASE_BAUD, SANDPOINT_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
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iomem_base: (u8 *)SANDPOINT_SERIAL_0, \
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io_type: SERIAL_IO_MEM }, \
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{ 0, BASE_BAUD, SANDPOINT_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
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iomem_base: (u8 *)SANDPOINT_SERIAL_1, \
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io_type: SERIAL_IO_MEM },
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#define SERIAL_PORT_DFNS \
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STD_SERIAL_PORT_DFNS
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#endif /* __PPC_PLATFORMS_SANDPOINT_H */
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