9aa753c442
The S3C2443 clock code could easily make use of the clksrc implementation in plat-samsung for many of the clocks. Make the clocks that easily move to clksrc-clk over, update any initialisation and remove the old register definitions from the header file (it is only being used once). Signed-off-by: Ben Dooks <ben-linux@fluff.org>
851 lines
19 KiB
C
851 lines
19 KiB
C
/* linux/arch/arm/mach-s3c2443/clock.c
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*
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* Copyright (c) 2007,2010 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2443 Clock control support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/sysdev.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/regs-s3c2443-clock.h>
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#include <plat/cpu-freq.h>
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#include <plat/s3c2443.h>
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/cpu.h>
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/* We currently have to assume that the system is running
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* from the XTPll input, and that all ***REFCLKs are being
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* fed from it, as we cannot read the state of OM[4] from
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* software.
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*
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* It would be possible for each board initialisation to
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* set the correct muxing at initialisation
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*/
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static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
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{
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u32 ctrlbit = clk->ctrlbit;
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u32 con = __raw_readl(reg);
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if (enable)
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con |= ctrlbit;
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else
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con &= ~ctrlbit;
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__raw_writel(con, reg);
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return 0;
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}
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static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
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}
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static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
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}
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static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
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}
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/* s3c2443_roundate_clksrc is close enough to s3c_roundate_clksrc */
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/* clock selections */
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static struct clk clk_mpllref = {
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.name = "mpllref",
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.parent = &clk_xtal,
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.id = -1,
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};
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#if 0
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static struct clk clk_mpll = {
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.name = "mpll",
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.parent = &clk_mpllref,
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.id = -1,
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};
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#endif
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static struct clk clk_i2s_ext = {
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.name = "i2s-ext",
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.id = -1,
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};
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static struct clk *clk_epllref_sources[] = {
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[0] = &clk_mpllref,
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[1] = &clk_mpllref,
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[2] = &clk_xtal,
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[3] = &clk_ext,
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};
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static struct clksrc_clk clk_epllref = {
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.clk = {
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.name = "epllref",
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.id = -1,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_epllref_sources,
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.nr_sources = ARRAY_SIZE(clk_epllref_sources),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
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};
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static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long div = __raw_readl(S3C2443_CLKDIV0);
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div &= S3C2443_CLKDIV0_EXTDIV_MASK;
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div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
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return parent_rate / (div + 1);
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}
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static struct clk clk_mdivclk = {
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.name = "mdivclk",
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.parent = &clk_mpllref,
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.id = -1,
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.ops = &(struct clk_ops) {
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.get_rate = s3c2443_getrate_mdivclk,
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},
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};
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static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
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clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL |
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S3C2443_CLKSRC_EXTCLK_DIV);
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if (parent == &clk_mpll)
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clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL;
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else if (parent == &clk_mdivclk)
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clksrc |= S3C2443_CLKSRC_EXTCLK_DIV;
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else if (parent != &clk_mpllref)
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return -EINVAL;
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__raw_writel(clksrc, S3C2443_CLKSRC);
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clk->parent = parent;
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return 0;
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}
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static struct clk clk_msysclk = {
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.name = "msysclk",
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.parent = &clk_xtal,
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.id = -1,
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.ops = &(struct clk_ops) {
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.set_parent = s3c2443_setparent_msysclk,
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},
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};
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/* armdiv
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*
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* this clock is sourced from msysclk and can have a number of
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* divider values applied to it to then be fed into armclk.
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*/
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static struct clk clk_armdiv = {
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.name = "armdiv",
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.id = -1,
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.parent = &clk_msysclk,
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};
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/* armclk
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*
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* this is the clock fed into the ARM core itself, either from
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* armdiv or from hclk.
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*/
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static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent)
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{
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unsigned long clkdiv0;
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clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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if (parent == &clk_armdiv)
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clkdiv0 &= ~S3C2443_CLKDIV0_DVS;
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else if (parent == &clk_h)
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clkdiv0 |= S3C2443_CLKDIV0_DVS;
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else
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return -EINVAL;
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__raw_writel(clkdiv0, S3C2443_CLKDIV0);
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return 0;
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}
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static struct clk clk_arm = {
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.name = "armclk",
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.id = -1,
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.ops = &(struct clk_ops) {
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.set_parent = s3c2443_setparent_armclk,
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},
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};
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/* esysclk
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*
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* this is sourced from either the EPLL or the EPLLref clock
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*/
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static int s3c2443_setparent_esysclk(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
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if (parent == &clk_epll)
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clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL;
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else if (parent == &clk_epllref.clk)
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clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL;
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else
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return -EINVAL;
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__raw_writel(clksrc, S3C2443_CLKSRC);
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clk->parent = parent;
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return 0;
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}
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static struct clk clk_esysclk = {
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.name = "esysclk",
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.parent = &clk_epll,
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.id = -1,
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.ops = &(struct clk_ops) {
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.set_parent = s3c2443_setparent_esysclk,
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},
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};
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/* uartclk
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*
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* UART baud-rate clock sourced from esysclk via a divisor
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*/
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static struct clksrc_clk clk_uart = {
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.clk = {
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.name = "uartclk",
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.id = -1,
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.parent = &clk_esysclk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
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};
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/* hsspi
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*
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* high-speed spi clock, sourced from esysclk
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*/
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static struct clksrc_clk clk_hsspi = {
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.clk = {
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.name = "hsspi",
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.id = -1,
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.parent = &clk_esysclk,
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.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
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};
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/* usbhost
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*
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* usb host bus-clock, usually 48MHz to provide USB bus clock timing
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*/
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static struct clksrc_clk clk_usb_bus_host = {
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.clk = {
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.name = "usb-bus-host-parent",
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.id = -1,
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.parent = &clk_esysclk,
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.ctrlbit = S3C2443_SCLKCON_USBHOST,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
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};
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/* clk_hsmcc_div
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*
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* this clock is sourced from epll, and is fed through a divider,
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* to a mux controlled by sclkcon where either it or a extclk can
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* be fed to the hsmmc block
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*/
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static struct clksrc_clk clk_hsmmc_div = {
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.clk = {
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.name = "hsmmc-div",
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.id = -1,
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.parent = &clk_esysclk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
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};
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static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
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clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
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S3C2443_SCLKCON_HSMMCCLK_EPLL);
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if (parent == &clk_epll)
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clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
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else if (parent == &clk_ext)
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clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
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else
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return -EINVAL;
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if (clk->usage > 0) {
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__raw_writel(clksrc, S3C2443_SCLKCON);
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}
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clk->parent = parent;
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return 0;
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}
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static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
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{
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return s3c2443_setparent_hsmmc(clk, clk->parent);
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}
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static struct clk clk_hsmmc = {
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.name = "hsmmc-if",
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.id = -1,
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.parent = &clk_hsmmc_div.clk,
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.enable = s3c2443_enable_hsmmc,
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.ops = &(struct clk_ops) {
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.set_parent = s3c2443_setparent_hsmmc,
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},
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};
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/* i2s_eplldiv
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*
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* This clock is the output from the I2S divisor of ESYSCLK, and is seperate
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* from the mux that comes after it (cannot merge into one single clock)
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*/
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static struct clksrc_clk clk_i2s_eplldiv = {
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.clk = {
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.name = "i2s-eplldiv",
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.id = -1,
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.parent = &clk_esysclk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
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};
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/* i2s-ref
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*
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* i2s bus reference clock, selectable from external, esysclk or epllref
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*
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* Note, this used to be two clocks, but was compressed into one.
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*/
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struct clk *clk_i2s_srclist[] = {
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[0] = &clk_i2s_eplldiv.clk,
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[1] = &clk_i2s_ext,
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[2] = &clk_epllref.clk,
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[3] = &clk_epllref.clk,
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};
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static struct clksrc_clk clk_i2s = {
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.clk = {
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.name = "i2s-if",
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.id = -1,
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.ctrlbit = S3C2443_SCLKCON_I2SCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_i2s_srclist,
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.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
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};
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/* cam-if
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*
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* camera interface bus-clock, divided down from esysclk
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*/
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static struct clksrc_clk clk_cam = {
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.clk = {
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.name = "camif-upll", /* same as 2440 name */
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.id = -1,
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.parent = &clk_esysclk,
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.ctrlbit = S3C2443_SCLKCON_CAMCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
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};
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/* display-if
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*
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* display interface clock, divided from esysclk
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*/
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static struct clksrc_clk clk_display = {
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.clk = {
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.name = "display-if",
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.id = -1,
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.parent = &clk_esysclk,
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.ctrlbit = S3C2443_SCLKCON_DISPCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
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};
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/* prediv
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*
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* this divides the msysclk down to pass to h/p/etc.
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*/
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static unsigned long s3c2443_prediv_getrate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
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clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
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return rate / (clkdiv0 + 1);
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}
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static struct clk clk_prediv = {
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.name = "prediv",
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.id = -1,
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.parent = &clk_msysclk,
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.ops = &(struct clk_ops) {
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.get_rate = s3c2443_prediv_getrate,
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},
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};
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/* standard clock definitions */
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static struct clk init_clocks_disable[] = {
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{
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.name = "nand",
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.id = -1,
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.parent = &clk_h,
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}, {
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.name = "sdi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_SDI,
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_ADC,
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}, {
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.name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIC,
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}, {
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.name = "iis",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIS,
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}, {
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.name = "spi",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_SPI0,
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}, {
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.name = "spi",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_SPI1,
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}
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};
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static struct clk init_clocks[] = {
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{
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.name = "dma",
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.id = 0,
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA0,
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}, {
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.name = "dma",
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.id = 1,
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA1,
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}, {
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.name = "dma",
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.id = 2,
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_DMA2,
|
|
}, {
|
|
.name = "dma",
|
|
.id = 3,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_DMA3,
|
|
}, {
|
|
.name = "dma",
|
|
.id = 4,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_DMA4,
|
|
}, {
|
|
.name = "dma",
|
|
.id = 5,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_DMA5,
|
|
}, {
|
|
.name = "lcd",
|
|
.id = -1,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_LCDC,
|
|
}, {
|
|
.name = "gpio",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_GPIO,
|
|
}, {
|
|
.name = "usb-host",
|
|
.id = -1,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_USBH,
|
|
}, {
|
|
.name = "usb-device",
|
|
.id = -1,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_USBD,
|
|
}, {
|
|
.name = "hsmmc",
|
|
.id = -1,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_HSMMC,
|
|
}, {
|
|
.name = "cfc",
|
|
.id = -1,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_CFC,
|
|
}, {
|
|
.name = "ssmc",
|
|
.id = -1,
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_SSMC,
|
|
}, {
|
|
.name = "timers",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_PWMT,
|
|
}, {
|
|
.name = "uart",
|
|
.id = 0,
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_UART0,
|
|
}, {
|
|
.name = "uart",
|
|
.id = 1,
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_UART1,
|
|
}, {
|
|
.name = "uart",
|
|
.id = 2,
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_UART2,
|
|
}, {
|
|
.name = "uart",
|
|
.id = 3,
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_UART3,
|
|
}, {
|
|
.name = "rtc",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_RTC,
|
|
}, {
|
|
.name = "watchdog",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.ctrlbit = S3C2443_PCLKCON_WDT,
|
|
}, {
|
|
.name = "usb-bus-host",
|
|
.id = -1,
|
|
.parent = &clk_usb_bus_host.clk,
|
|
}, {
|
|
.name = "ac97",
|
|
.id = -1,
|
|
.parent = &clk_p,
|
|
.ctrlbit = S3C2443_PCLKCON_AC97,
|
|
}
|
|
};
|
|
|
|
/* clocks to add where we need to check their parentage */
|
|
|
|
/* s3c2443_clk_initparents
|
|
*
|
|
* Initialise the parents for the clocks that we get at start-time
|
|
*/
|
|
|
|
static int __init clk_init_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
printk(KERN_DEBUG "clock %s: parent %s\n", clk->name, parent->name);
|
|
return clk_set_parent(clk, parent);
|
|
}
|
|
|
|
static struct clksrc_clk __initdata *init_list[] = {
|
|
&clk_epllref, /* should be first */
|
|
&clk_i2s_eplldiv,
|
|
&clk_i2s,
|
|
&clk_cam,
|
|
&clk_uart,
|
|
&clk_display,
|
|
&clk_hsmmc_div,
|
|
&clk_usb_bus_host,
|
|
};
|
|
|
|
static void __init s3c2443_clk_initparents(void)
|
|
{
|
|
unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
|
|
struct clk *parent;
|
|
int ptr;
|
|
|
|
/* esysclk source */
|
|
|
|
parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ?
|
|
&clk_epll : &clk_epllref.clk;
|
|
|
|
clk_init_set_parent(&clk_esysclk, parent);
|
|
|
|
/* msysclk source */
|
|
|
|
if (clksrc & S3C2443_CLKSRC_MSYSCLK_MPLL) {
|
|
parent = &clk_mpll;
|
|
} else {
|
|
parent = (clksrc & S3C2443_CLKSRC_EXTCLK_DIV) ?
|
|
&clk_mdivclk : &clk_mpllref;
|
|
}
|
|
|
|
clk_init_set_parent(&clk_msysclk, parent);
|
|
|
|
/* arm */
|
|
|
|
if (__raw_readl(S3C2443_CLKDIV0) & S3C2443_CLKDIV0_DVS)
|
|
parent = &clk_h;
|
|
else
|
|
parent = &clk_armdiv;
|
|
|
|
clk_init_set_parent(&clk_arm, parent);
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_list); ptr++)
|
|
s3c_set_clksrc(init_list[ptr], false);
|
|
}
|
|
|
|
/* armdiv divisor table */
|
|
|
|
static unsigned int armdiv[16] = {
|
|
[S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
|
|
[S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
|
|
[S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
|
|
[S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
|
|
[S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
|
|
[S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
|
|
[S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
|
|
[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
|
|
};
|
|
|
|
static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
|
|
{
|
|
clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
|
|
|
|
return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
|
|
}
|
|
|
|
static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
|
|
{
|
|
clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
|
|
|
|
return clkcon0 + 1;
|
|
}
|
|
|
|
/* clocks to add straight away */
|
|
|
|
static struct clksrc_clk *clksrcs[] __initdata = {
|
|
&clk_usb_bus_host,
|
|
&clk_epllref,
|
|
&clk_uart,
|
|
&clk_display,
|
|
&clk_cam,
|
|
&clk_i2s_eplldiv,
|
|
&clk_i2s,
|
|
&clk_hsspi,
|
|
&clk_hsmmc_div,
|
|
};
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
&clk_ext,
|
|
&clk_epll,
|
|
&clk_usb_bus,
|
|
&clk_esysclk,
|
|
&clk_mpllref,
|
|
&clk_msysclk,
|
|
&clk_hsmmc,
|
|
&clk_armdiv,
|
|
&clk_arm,
|
|
&clk_prediv,
|
|
};
|
|
|
|
void __init_or_cpufreq s3c2443_setup_clocks(void)
|
|
{
|
|
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
|
|
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
|
|
struct clk *xtal_clk;
|
|
unsigned long xtal;
|
|
unsigned long pll;
|
|
unsigned long fclk;
|
|
unsigned long hclk;
|
|
unsigned long pclk;
|
|
|
|
xtal_clk = clk_get(NULL, "xtal");
|
|
xtal = clk_get_rate(xtal_clk);
|
|
clk_put(xtal_clk);
|
|
|
|
pll = s3c2443_get_mpll(mpllcon, xtal);
|
|
clk_msysclk.rate = pll;
|
|
|
|
fclk = pll / s3c2443_fclk_div(clkdiv0);
|
|
hclk = s3c2443_prediv_getrate(&clk_prediv);
|
|
hclk /= s3c2443_get_hdiv(clkdiv0);
|
|
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
|
|
|
|
s3c24xx_setup_clocks(fclk, hclk, pclk);
|
|
|
|
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
|
|
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
|
|
print_mhz(pll), print_mhz(fclk),
|
|
print_mhz(hclk), print_mhz(pclk));
|
|
|
|
s3c24xx_setup_clocks(fclk, hclk, pclk);
|
|
}
|
|
|
|
void __init s3c2443_init_clocks(int xtal)
|
|
{
|
|
struct clk *clkp;
|
|
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
|
|
int ret;
|
|
int ptr;
|
|
|
|
/* s3c2443 parents h and p clocks from prediv */
|
|
clk_h.parent = &clk_prediv;
|
|
clk_p.parent = &clk_prediv;
|
|
|
|
s3c24xx_register_baseclocks(xtal);
|
|
s3c2443_setup_clocks();
|
|
s3c2443_clk_initparents();
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
|
|
clkp = clks[ptr];
|
|
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
}
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
|
|
s3c_register_clksrc(clksrcs[ptr], 1);
|
|
|
|
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
|
|
clk_epll.parent = &clk_epllref.clk;
|
|
clk_usb_bus.parent = &clk_usb_bus_host.clk;
|
|
|
|
/* ensure usb bus clock is within correct rate of 48MHz */
|
|
|
|
if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
|
|
printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
|
|
clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
|
|
}
|
|
|
|
printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
|
|
(epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
|
|
print_mhz(clk_get_rate(&clk_epll)),
|
|
print_mhz(clk_get_rate(&clk_usb_bus)));
|
|
|
|
/* register clocks from clock array */
|
|
|
|
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
|
|
|
/* We must be careful disabling the clocks we are not intending to
|
|
* be using at boot time, as subsystems such as the LCD which do
|
|
* their own DMA requests to the bus can cause the system to lockup
|
|
* if they where in the middle of requesting bus access.
|
|
*
|
|
* Disabling the LCD clock if the LCD is active is very dangerous,
|
|
* and therefore the bootloader should be careful to not enable
|
|
* the LCD clock if it is not needed.
|
|
*/
|
|
|
|
/* install (and disable) the clocks we do not need immediately */
|
|
|
|
clkp = init_clocks_disable;
|
|
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
|
|
|
|
ret = s3c24xx_register_clock(clkp);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
|
clkp->name, ret);
|
|
}
|
|
|
|
(clkp->enable)(clkp, 0);
|
|
}
|
|
|
|
s3c_pwmclk_init();
|
|
}
|