5026dafa17
On Tilera Gx72 systems, the logic for figuring out whether a given port is root complex is slightly different. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
199 lines
6.9 KiB
C
199 lines
6.9 KiB
C
/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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/**
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* Interface definitions for the trio driver.
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*/
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#ifndef _SYS_HV_DRV_TRIO_INTF_H
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#define _SYS_HV_DRV_TRIO_INTF_H
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#include <arch/trio.h>
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/** The vendor ID for all Tilera processors. */
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#define TILERA_VENDOR_ID 0x1a41
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/** The device ID for the Gx36 processor. */
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#define TILERA_GX36_DEV_ID 0x0200
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/** Device ID for our internal bridge when running as RC. */
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#define TILERA_GX36_RC_DEV_ID 0x2000
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/** Maximum number of TRIO interfaces. */
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#define TILEGX_NUM_TRIO 2
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/** Gx36 has max 3 PCIe MACs per TRIO interface. */
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#define TILEGX_TRIO_PCIES 3
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/** Specify port properties for a PCIe MAC. */
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struct pcie_port_property
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{
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/** If true, the link can be configured in PCIe root complex mode. */
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uint8_t allow_rc: 1;
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/** If true, the link can be configured in PCIe endpoint mode. */
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uint8_t allow_ep: 1;
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/** If true, the link can be configured in StreamIO mode. */
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uint8_t allow_sio: 1;
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/** If true, the link is allowed to support 1-lane operation. Software
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* will not consider it an error if the link comes up as a x1 link. */
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uint8_t allow_x1: 1;
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/** If true, the link is allowed to support 2-lane operation. Software
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* will not consider it an error if the link comes up as a x2 link. */
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uint8_t allow_x2: 1;
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/** If true, the link is allowed to support 4-lane operation. Software
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* will not consider it an error if the link comes up as a x4 link. */
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uint8_t allow_x4: 1;
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/** If true, the link is allowed to support 8-lane operation. Software
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* will not consider it an error if the link comes up as a x8 link. */
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uint8_t allow_x8: 1;
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/** If true, this link is connected to a device which may or may not
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* be present. */
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uint8_t removable: 1;
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};
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/** Configurations can be issued to configure a char stream interrupt. */
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typedef enum pcie_stream_intr_config_sel_e
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{
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/** Interrupt configuration for memory map regions. */
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MEM_MAP_SEL,
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/** Interrupt configuration for push DMAs. */
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PUSH_DMA_SEL,
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/** Interrupt configuration for pull DMAs. */
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PULL_DMA_SEL,
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}
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pcie_stream_intr_config_sel_t;
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/** The mmap file offset (PA) of the TRIO config region. */
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#define HV_TRIO_CONFIG_OFFSET \
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((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_CFG << \
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TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT)
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/** The maximum size of the TRIO config region. */
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#define HV_TRIO_CONFIG_SIZE \
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(1ULL << TRIO_CFG_REGION_ADDR__REGION_SHIFT)
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/** Size of the config region mapped into client. We can't use
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* TRIO_MMIO_ADDRESS_SPACE__OFFSET_WIDTH because it
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* will require the kernel to allocate 4GB VA space
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* from the VMALLOC region which has a total range
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* of 4GB.
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*/
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#define HV_TRIO_CONFIG_IOREMAP_SIZE \
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((uint64_t) 1 << TRIO_CFG_REGION_ADDR__PROT_SHIFT)
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/** The mmap file offset (PA) of a scatter queue region. */
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#define HV_TRIO_SQ_OFFSET(queue) \
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(((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_SQ << \
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TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
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((queue) << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT))
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/** The maximum size of a scatter queue region. */
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#define HV_TRIO_SQ_SIZE \
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(1ULL << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT)
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/** The "hardware MMIO region" of the first PIO region. */
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#define HV_TRIO_FIRST_PIO_REGION 8
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/** The mmap file offset (PA) of a PIO region. */
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#define HV_TRIO_PIO_OFFSET(region) \
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(((unsigned long long)(region) + HV_TRIO_FIRST_PIO_REGION) \
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<< TRIO_PIO_REGIONS_ADDR__REGION_SHIFT)
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/** The maximum size of a PIO region. */
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#define HV_TRIO_PIO_SIZE (1ULL << TRIO_PIO_REGIONS_ADDR__ADDR_WIDTH)
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/** The mmap file offset (PA) of a push DMA region. */
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#define HV_TRIO_PUSH_DMA_OFFSET(ring) \
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(((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PUSH_DMA << \
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TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
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((ring) << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT))
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/** The mmap file offset (PA) of a pull DMA region. */
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#define HV_TRIO_PULL_DMA_OFFSET(ring) \
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(((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PULL_DMA << \
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TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
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((ring) << TRIO_PULL_DMA_REGION_ADDR__RING_SEL_SHIFT))
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/** The maximum size of a DMA region. */
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#define HV_TRIO_DMA_REGION_SIZE \
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(1ULL << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT)
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/** The mmap file offset (PA) of a Mem-Map interrupt region. */
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#define HV_TRIO_MEM_MAP_INTR_OFFSET(map) \
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(((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_MEM << \
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TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
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((map) << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT))
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/** The maximum size of a Mem-Map interrupt region. */
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#define HV_TRIO_MEM_MAP_INTR_SIZE \
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(1ULL << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT)
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/** A flag bit indicating a fixed resource allocation. */
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#define HV_TRIO_ALLOC_FIXED 0x01
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/** TRIO requires that all mappings have 4kB aligned start addresses. */
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#define HV_TRIO_PAGE_SHIFT 12
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/** TRIO requires that all mappings have 4kB aligned start addresses. */
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#define HV_TRIO_PAGE_SIZE (1ull << HV_TRIO_PAGE_SHIFT)
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/* Specify all PCIe port properties for a TRIO. */
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struct pcie_trio_ports_property
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{
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struct pcie_port_property ports[TILEGX_TRIO_PCIES];
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/** Set if this TRIO belongs to a Gx72 device. */
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uint8_t is_gx72;
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};
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/* Flags indicating traffic class. */
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#define HV_TRIO_FLAG_TC_SHIFT 4
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#define HV_TRIO_FLAG_TC_RMASK 0xf
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#define HV_TRIO_FLAG_TC(N) \
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((((N) & HV_TRIO_FLAG_TC_RMASK) + 1) << HV_TRIO_FLAG_TC_SHIFT)
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/* Flags indicating virtual functions. */
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#define HV_TRIO_FLAG_VFUNC_SHIFT 8
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#define HV_TRIO_FLAG_VFUNC_RMASK 0xff
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#define HV_TRIO_FLAG_VFUNC(N) \
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((((N) & HV_TRIO_FLAG_VFUNC_RMASK) + 1) << HV_TRIO_FLAG_VFUNC_SHIFT)
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/* Flag indicating an ordered PIO region. */
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#define HV_TRIO_PIO_FLAG_ORDERED (1 << 16)
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/* Flags indicating special types of PIO regions. */
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#define HV_TRIO_PIO_FLAG_SPACE_SHIFT 17
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#define HV_TRIO_PIO_FLAG_SPACE_MASK (0x3 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
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#define HV_TRIO_PIO_FLAG_CONFIG_SPACE (0x1 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
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#define HV_TRIO_PIO_FLAG_IO_SPACE (0x2 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
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#endif /* _SYS_HV_DRV_TRIO_INTF_H */
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