b01cc1b0ea
This converts the remaining x86 clocksources to use clocksource_register_hz/khz. CC: jacob.jun.pan@intel.com CC: Glauber Costa <glommer@redhat.com> CC: Dimitri Sivanich <sivanich@sgi.com> CC: Rusty Russell <rusty@rustcorp.com.au> CC: Jeremy Fitzhardinge <jeremy@xensource.com> CC: Chris McDermott <lcm@us.ibm.com> CC: Thomas Gleixner <tglx@linutronix.de> Tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> [xen] Signed-off-by: John Stultz <johnstul@us.ibm.com>
113 lines
2.9 KiB
C
113 lines
2.9 KiB
C
#include <linux/clocksource.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/timex.h>
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#include <linux/init.h>
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#include <asm/pgtable.h>
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#include <asm/io.h>
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#include <asm/mach_timer.h>
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#define CYCLONE_CBAR_ADDR 0xFEB00CD0 /* base address ptr */
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#define CYCLONE_PMCC_OFFSET 0x51A0 /* offset to control register */
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#define CYCLONE_MPCS_OFFSET 0x51A8 /* offset to select register */
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#define CYCLONE_MPMC_OFFSET 0x51D0 /* offset to count register */
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#define CYCLONE_TIMER_FREQ 99780000 /* 100Mhz, but not really */
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#define CYCLONE_TIMER_MASK CLOCKSOURCE_MASK(32) /* 32 bit mask */
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int use_cyclone = 0;
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static void __iomem *cyclone_ptr;
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static cycle_t read_cyclone(struct clocksource *cs)
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{
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return (cycle_t)readl(cyclone_ptr);
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}
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static struct clocksource clocksource_cyclone = {
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.name = "cyclone",
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.rating = 250,
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.read = read_cyclone,
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.mask = CYCLONE_TIMER_MASK,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init init_cyclone_clocksource(void)
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{
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unsigned long base; /* saved value from CBAR */
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unsigned long offset;
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u32 __iomem* volatile cyclone_timer; /* Cyclone MPMC0 register */
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u32 __iomem* reg;
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int i;
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/* make sure we're on a summit box: */
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if (!use_cyclone)
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return -ENODEV;
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printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
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/* find base address: */
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offset = CYCLONE_CBAR_ADDR;
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reg = ioremap_nocache(offset, sizeof(reg));
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if (!reg) {
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printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
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return -ENODEV;
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}
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/* even on 64bit systems, this is only 32bits: */
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base = readl(reg);
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if (!base) {
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printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
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return -ENODEV;
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}
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iounmap(reg);
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/* setup PMCC: */
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offset = base + CYCLONE_PMCC_OFFSET;
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reg = ioremap_nocache(offset, sizeof(reg));
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if (!reg) {
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printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
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return -ENODEV;
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}
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writel(0x00000001,reg);
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iounmap(reg);
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/* setup MPCS: */
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offset = base + CYCLONE_MPCS_OFFSET;
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reg = ioremap_nocache(offset, sizeof(reg));
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if (!reg) {
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printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
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return -ENODEV;
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}
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writel(0x00000001,reg);
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iounmap(reg);
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/* map in cyclone_timer: */
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offset = base + CYCLONE_MPMC_OFFSET;
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cyclone_timer = ioremap_nocache(offset, sizeof(u64));
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if (!cyclone_timer) {
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printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
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return -ENODEV;
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}
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/* quick test to make sure its ticking: */
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for (i = 0; i < 3; i++){
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u32 old = readl(cyclone_timer);
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int stall = 100;
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while (stall--)
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barrier();
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if (readl(cyclone_timer) == old) {
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printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
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iounmap(cyclone_timer);
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cyclone_timer = NULL;
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return -ENODEV;
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}
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}
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cyclone_ptr = cyclone_timer;
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return clocksource_register_hz(&clocksource_cyclone,
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CYCLONE_TIMER_FREQ);
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}
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arch_initcall(init_cyclone_clocksource);
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