999304be11
This patch adds setup code for Samsung OneNAND controller driver. The driver needs to be aware on which SoC it is running, so the actual device id is being changed in cpu init code. S3C64xx SoCs have 2 OneNAND controllers while S5PC100 and S5PC110 has only one. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [ben-linux@fluff.org: sort map.h entries] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
158 lines
4.8 KiB
C
158 lines
4.8 KiB
C
/* linux/arch/arm/mach-s5pc100/include/mach/map.h
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*
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* Copyright 2009 Samsung Electronics Co.
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* Byungho Min <bhmin@samsung.com>
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*
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* Based on mach-s3c6400/include/mach/map.h
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*
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* S5PC1XX - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H __FILE__
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#include <plat/map-base.h>
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/*
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* map-base.h has already defined virtual memory address
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* S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
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* S3C_VA_SYS S3C_ADDR(0x00100000) system control
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* S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
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* S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
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* S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
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* S3C_VA_UART S3C_ADDR(0x01000000) UART
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*
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* S5PC100 specific virtual memory address can be defined here
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* S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
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*
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*/
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#define S5PC100_PA_ONENAND_BUF (0xB0000000)
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#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
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/* Chip ID */
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#define S5PC100_PA_CHIPID (0xE0000000)
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#define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID
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#define S5PC1XX_VA_CHIPID S3C_VA_SYS
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/* System */
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#define S5PC100_PA_CLK (0xE0100000)
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#define S5PC100_PA_CLK_OTHER (0xE0200000)
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#define S5PC100_PA_PWR (0xE0108000)
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#define S5PC1XX_PA_CLK S5PC100_PA_CLK
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#define S5PC1XX_PA_PWR S5PC100_PA_PWR
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#define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER
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#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000)
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#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000)
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#define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000)
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/* GPIO */
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#define S5PC100_PA_GPIO (0xE0300000)
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#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO
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#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
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/* Interrupt */
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#define S5PC100_PA_VIC (0xE4000000)
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#define S5PC100_VA_VIC S3C_VA_IRQ
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#define S5PC100_PA_VIC_OFFSET 0x100000
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#define S5PC100_VA_VIC_OFFSET 0x10000
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#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
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#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
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#define S5PC100_PA_ONENAND (0xE7100000)
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/* DMA */
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#define S5PC100_PA_MDMA (0xE8100000)
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#define S5PC100_PA_PDMA0 (0xE9000000)
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#define S5PC100_PA_PDMA1 (0xE9200000)
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/* Timer */
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#define S5PC100_PA_TIMER (0xEA000000)
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#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER
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#define S5PC1XX_VA_TIMER S3C_VA_TIMER
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/* RTC */
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#define S5PC100_PA_RTC (0xEA300000)
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/* UART */
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#define S5PC100_PA_UART (0xEC000000)
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#define S5PC1XX_PA_UART S5PC100_PA_UART
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#define S5PC1XX_VA_UART S3C_VA_UART
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/* I2C */
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#define S5PC100_PA_I2C (0xEC100000)
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#define S5PC100_PA_I2C1 (0xEC200000)
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/* USB HS OTG */
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#define S5PC100_PA_USB_HSOTG (0xED200000)
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#define S5PC100_PA_USB_HSPHY (0xED300000)
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/* SD/MMC */
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#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
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#define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0)
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#define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1)
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#define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2)
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/* LCD */
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#define S5PC100_PA_FB (0xEE000000)
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/* Multimedia */
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#define S5PC100_PA_G2D (0xEE800000)
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#define S5PC100_PA_JPEG (0xEE500000)
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#define S5PC100_PA_ROTATOR (0xEE100000)
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#define S5PC100_PA_G3D (0xEF000000)
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/* I2S */
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#define S5PC100_PA_I2S0 (0xF2000000)
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#define S5PC100_PA_I2S1 (0xF2100000)
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#define S5PC100_PA_I2S2 (0xF2200000)
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/* KEYPAD */
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#define S5PC100_PA_KEYPAD (0xF3100000)
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/* ADC & TouchScreen */
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#define S5PC100_PA_TSADC (0xF3000000)
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/* ETC */
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#define S5PC100_PA_SDRAM (0x20000000)
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#define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM
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/* compatibility defines. */
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#define S3C_PA_RTC S5PC100_PA_RTC
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#define S3C_PA_UART S5PC100_PA_UART
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#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0)
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#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400)
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#define S3C_PA_UART2 (S5PC100_PA_UART + 0x800)
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#define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00)
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#define S3C_VA_UART0 (S3C_VA_UART + 0x0)
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#define S3C_VA_UART1 (S3C_VA_UART + 0x400)
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#define S3C_VA_UART2 (S3C_VA_UART + 0x800)
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#define S3C_VA_UART3 (S3C_VA_UART + 0xC00)
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#define S3C_UART_OFFSET 0x400
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#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
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#define S3C_PA_FB S5PC100_PA_FB
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#define S3C_PA_G2D S5PC100_PA_G2D
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#define S3C_PA_G3D S5PC100_PA_G3D
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#define S3C_PA_JPEG S5PC100_PA_JPEG
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#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
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#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0)
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#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
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#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000)
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#define S3C_PA_IIC S5PC100_PA_I2C
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#define S3C_PA_IIC1 S5PC100_PA_I2C1
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#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
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#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
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#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0
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#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1
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#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2
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#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
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#define S3C_PA_TSADC S5PC100_PA_TSADC
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#define S3C_PA_ONENAND S5PC100_PA_ONENAND
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#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
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#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
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#endif /* __ASM_ARCH_C100_MAP_H */
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