d3c977927b
Because of a typo, incorrect field of a structure was being checked. This patch fixes the check to use correct field. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
579 lines
17 KiB
C
579 lines
17 KiB
C
/*
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* Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* http://www.linaro.org
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*
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This file contains the Samsung Exynos specific information required by the
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* the Samsung pinctrl/gpiolib driver. It also includes the implementation of
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* external gpio and wakeup interrupt support.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <asm/mach/irq.h>
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#include "pinctrl-samsung.h"
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#include "pinctrl-exynos.h"
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/* list of external wakeup controllers supported */
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static const struct of_device_id exynos_wkup_irq_ids[] = {
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{ .compatible = "samsung,exynos4210-wakeup-eint", },
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};
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static void exynos_gpio_irq_unmask(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
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struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
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unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
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unsigned long mask;
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mask = readl(d->virt_base + reg_mask);
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mask &= ~(1 << edata->pin);
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writel(mask, d->virt_base + reg_mask);
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}
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static void exynos_gpio_irq_mask(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
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struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
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unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
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unsigned long mask;
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mask = readl(d->virt_base + reg_mask);
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mask |= 1 << edata->pin;
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writel(mask, d->virt_base + reg_mask);
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}
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static void exynos_gpio_irq_ack(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
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struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
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unsigned long reg_pend = d->ctrl->geint_pend + edata->eint_offset;
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writel(1 << edata->pin, d->virt_base + reg_pend);
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}
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static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
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struct samsung_pin_ctrl *ctrl = d->ctrl;
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struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
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struct samsung_pin_bank *bank = edata->bank;
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unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
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unsigned int con, trig_type;
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unsigned long reg_con = ctrl->geint_con + edata->eint_offset;
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unsigned int mask;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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trig_type = EXYNOS_EINT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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trig_type = EXYNOS_EINT_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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trig_type = EXYNOS_EINT_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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trig_type = EXYNOS_EINT_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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trig_type = EXYNOS_EINT_LEVEL_LOW;
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break;
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default:
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pr_err("unsupported external interrupt type\n");
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return -EINVAL;
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}
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if (type & IRQ_TYPE_EDGE_BOTH)
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__irq_set_handler_locked(irqd->irq, handle_edge_irq);
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else
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__irq_set_handler_locked(irqd->irq, handle_level_irq);
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con = readl(d->virt_base + reg_con);
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con &= ~(EXYNOS_EINT_CON_MASK << shift);
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con |= trig_type << shift;
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writel(con, d->virt_base + reg_con);
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reg_con = bank->pctl_offset;
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shift = edata->pin * bank->func_width;
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mask = (1 << bank->func_width) - 1;
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con = readl(d->virt_base + reg_con);
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con &= ~(mask << shift);
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con |= EXYNOS_EINT_FUNC << shift;
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writel(con, d->virt_base + reg_con);
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return 0;
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}
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/*
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* irq_chip for gpio interrupts.
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*/
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static struct irq_chip exynos_gpio_irq_chip = {
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.name = "exynos_gpio_irq_chip",
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.irq_unmask = exynos_gpio_irq_unmask,
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.irq_mask = exynos_gpio_irq_mask,
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.irq_ack = exynos_gpio_irq_ack,
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.irq_set_type = exynos_gpio_irq_set_type,
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};
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/*
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* given a controller-local external gpio interrupt number, prepare the handler
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* data for it.
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*/
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static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
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struct samsung_pinctrl_drv_data *d)
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{
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struct samsung_pin_bank *bank = d->ctrl->pin_banks;
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struct exynos_geint_data *eint_data;
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unsigned int nr_banks = d->ctrl->nr_banks, idx;
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unsigned int irq_base = 0, eint_offset = 0;
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if (hw >= d->ctrl->nr_gint) {
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dev_err(d->dev, "unsupported ext-gpio interrupt\n");
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return NULL;
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}
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for (idx = 0; idx < nr_banks; idx++, bank++) {
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if (bank->eint_type != EINT_TYPE_GPIO)
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continue;
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if ((hw >= irq_base) && (hw < (irq_base + bank->nr_pins)))
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break;
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irq_base += bank->nr_pins;
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eint_offset += 4;
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}
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if (idx == nr_banks) {
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dev_err(d->dev, "pin bank not found for ext-gpio interrupt\n");
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return NULL;
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}
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eint_data = devm_kzalloc(d->dev, sizeof(*eint_data), GFP_KERNEL);
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if (!eint_data) {
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dev_err(d->dev, "no memory for eint-gpio data\n");
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return NULL;
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}
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eint_data->bank = bank;
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eint_data->pin = hw - irq_base;
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eint_data->eint_offset = eint_offset;
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return eint_data;
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}
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static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct samsung_pinctrl_drv_data *d = h->host_data;
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struct exynos_geint_data *eint_data;
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eint_data = exynos_get_eint_data(hw, d);
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if (!eint_data)
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return -EINVAL;
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irq_set_handler_data(virq, eint_data);
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
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handle_level_irq);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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static void exynos_gpio_irq_unmap(struct irq_domain *h, unsigned int virq)
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{
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struct samsung_pinctrl_drv_data *d = h->host_data;
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struct exynos_geint_data *eint_data;
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eint_data = irq_get_handler_data(virq);
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devm_kfree(d->dev, eint_data);
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}
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/*
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* irq domain callbacks for external gpio interrupt controller.
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*/
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static const struct irq_domain_ops exynos_gpio_irqd_ops = {
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.map = exynos_gpio_irq_map,
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.unmap = exynos_gpio_irq_unmap,
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.xlate = irq_domain_xlate_twocell,
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};
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static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
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{
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struct samsung_pinctrl_drv_data *d = data;
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struct samsung_pin_ctrl *ctrl = d->ctrl;
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struct samsung_pin_bank *bank = ctrl->pin_banks;
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unsigned int svc, group, pin, virq;
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svc = readl(d->virt_base + ctrl->svc);
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group = EXYNOS_SVC_GROUP(svc);
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pin = svc & EXYNOS_SVC_NUM_MASK;
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if (!group)
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return IRQ_HANDLED;
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bank += (group - 1);
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virq = irq_linear_revmap(d->gpio_irqd, bank->irq_base + pin);
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if (!virq)
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return IRQ_NONE;
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generic_handle_irq(virq);
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return IRQ_HANDLED;
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}
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/*
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* exynos_eint_gpio_init() - setup handling of external gpio interrupts.
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* @d: driver data of samsung pinctrl driver.
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*/
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static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
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{
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struct device *dev = d->dev;
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unsigned int ret;
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if (!d->irq) {
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dev_err(dev, "irq number not available\n");
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return -EINVAL;
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}
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ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
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0, dev_name(dev), d);
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if (ret) {
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dev_err(dev, "irq request failed\n");
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return -ENXIO;
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}
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d->gpio_irqd = irq_domain_add_linear(dev->of_node, d->ctrl->nr_gint,
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&exynos_gpio_irqd_ops, d);
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if (!d->gpio_irqd) {
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dev_err(dev, "gpio irq domain allocation failed\n");
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return -ENXIO;
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}
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return 0;
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}
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static void exynos_wkup_irq_unmask(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
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unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
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unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
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unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
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unsigned long mask;
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mask = readl(d->virt_base + reg_mask);
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mask &= ~(1 << pin);
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writel(mask, d->virt_base + reg_mask);
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}
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static void exynos_wkup_irq_mask(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
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unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
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unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
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unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
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unsigned long mask;
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mask = readl(d->virt_base + reg_mask);
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mask |= 1 << pin;
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writel(mask, d->virt_base + reg_mask);
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}
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static void exynos_wkup_irq_ack(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
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unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
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unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
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unsigned long pend = d->ctrl->weint_pend + (bank << 2);
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writel(1 << pin, d->virt_base + pend);
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}
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static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
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unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
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unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
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unsigned long reg_con = d->ctrl->weint_con + (bank << 2);
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unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
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unsigned long con, trig_type;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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trig_type = EXYNOS_EINT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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trig_type = EXYNOS_EINT_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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trig_type = EXYNOS_EINT_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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trig_type = EXYNOS_EINT_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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trig_type = EXYNOS_EINT_LEVEL_LOW;
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break;
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default:
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pr_err("unsupported external interrupt type\n");
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return -EINVAL;
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}
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if (type & IRQ_TYPE_EDGE_BOTH)
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__irq_set_handler_locked(irqd->irq, handle_edge_irq);
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else
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__irq_set_handler_locked(irqd->irq, handle_level_irq);
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con = readl(d->virt_base + reg_con);
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con &= ~(EXYNOS_EINT_CON_MASK << shift);
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con |= trig_type << shift;
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writel(con, d->virt_base + reg_con);
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return 0;
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}
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/*
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* irq_chip for wakeup interrupts
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*/
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static struct irq_chip exynos_wkup_irq_chip = {
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.name = "exynos_wkup_irq_chip",
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.irq_unmask = exynos_wkup_irq_unmask,
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.irq_mask = exynos_wkup_irq_mask,
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.irq_ack = exynos_wkup_irq_ack,
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.irq_set_type = exynos_wkup_irq_set_type,
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};
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/* interrupt handler for wakeup interrupts 0..15 */
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static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
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{
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struct exynos_weint_data *eintd = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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int eint_irq;
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chained_irq_enter(chip, desc);
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chip->irq_mask(&desc->irq_data);
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if (chip->irq_ack)
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chip->irq_ack(&desc->irq_data);
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eint_irq = irq_linear_revmap(eintd->domain, eintd->irq);
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generic_handle_irq(eint_irq);
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chip->irq_unmask(&desc->irq_data);
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chained_irq_exit(chip, desc);
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}
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static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend,
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struct irq_domain *domain)
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{
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unsigned int irq;
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while (pend) {
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irq = fls(pend) - 1;
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generic_handle_irq(irq_find_mapping(domain, irq_base + irq));
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pend &= ~(1 << irq);
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}
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}
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/* interrupt handler for wakeup interrupt 16 */
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static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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struct exynos_weint_data *eintd = irq_get_handler_data(irq);
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struct samsung_pinctrl_drv_data *d = eintd->domain->host_data;
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unsigned long pend;
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unsigned long mask;
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chained_irq_enter(chip, desc);
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pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8);
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mask = readl(d->virt_base + d->ctrl->weint_mask + 0x8);
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exynos_irq_demux_eint(16, pend & ~mask, eintd->domain);
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pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC);
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mask = readl(d->virt_base + d->ctrl->weint_mask + 0xC);
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exynos_irq_demux_eint(24, pend & ~mask, eintd->domain);
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chained_irq_exit(chip, desc);
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}
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static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq);
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irq_set_chip_data(virq, h->host_data);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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/*
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* irq domain callbacks for external wakeup interrupt controller.
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*/
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static const struct irq_domain_ops exynos_wkup_irqd_ops = {
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.map = exynos_wkup_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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/*
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* exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
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* @d: driver data of samsung pinctrl driver.
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*/
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static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
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{
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struct device *dev = d->dev;
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struct device_node *wkup_np = NULL;
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struct device_node *np;
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struct exynos_weint_data *weint_data;
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int idx, irq;
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for_each_child_of_node(dev->of_node, np) {
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if (of_match_node(exynos_wkup_irq_ids, np)) {
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wkup_np = np;
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break;
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}
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}
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if (!wkup_np)
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return -ENODEV;
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d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint,
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&exynos_wkup_irqd_ops, d);
|
|
if (!d->wkup_irqd) {
|
|
dev_err(dev, "wakeup irq domain allocation failed\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL);
|
|
if (!weint_data) {
|
|
dev_err(dev, "could not allocate memory for weint_data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
irq = irq_of_parse_and_map(wkup_np, 16);
|
|
if (irq) {
|
|
weint_data[16].domain = d->wkup_irqd;
|
|
irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
|
|
irq_set_handler_data(irq, &weint_data[16]);
|
|
} else {
|
|
dev_err(dev, "irq number for EINT16-32 not found\n");
|
|
}
|
|
|
|
for (idx = 0; idx < 16; idx++) {
|
|
weint_data[idx].domain = d->wkup_irqd;
|
|
weint_data[idx].irq = idx;
|
|
|
|
irq = irq_of_parse_and_map(wkup_np, idx);
|
|
if (irq) {
|
|
irq_set_handler_data(irq, &weint_data[idx]);
|
|
irq_set_chained_handler(irq, exynos_irq_eint0_15);
|
|
} else {
|
|
dev_err(dev, "irq number for eint-%x not found\n", idx);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* pin banks of exynos4210 pin-controller 0 */
|
|
static struct samsung_pin_bank exynos4210_pin_banks0[] = {
|
|
EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"),
|
|
EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"),
|
|
EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"),
|
|
EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"),
|
|
EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"),
|
|
EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"),
|
|
EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"),
|
|
EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"),
|
|
EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"),
|
|
EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"),
|
|
EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"),
|
|
EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"),
|
|
EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"),
|
|
EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"),
|
|
EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"),
|
|
EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"),
|
|
};
|
|
|
|
/* pin banks of exynos4210 pin-controller 1 */
|
|
static struct samsung_pin_bank exynos4210_pin_banks1[] = {
|
|
EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"),
|
|
EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"),
|
|
EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"),
|
|
EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"),
|
|
EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"),
|
|
EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"),
|
|
EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"),
|
|
EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"),
|
|
EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"),
|
|
EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"),
|
|
EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"),
|
|
EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"),
|
|
EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"),
|
|
EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"),
|
|
EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"),
|
|
EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"),
|
|
EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"),
|
|
EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"),
|
|
EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"),
|
|
EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"),
|
|
};
|
|
|
|
/* pin banks of exynos4210 pin-controller 2 */
|
|
static struct samsung_pin_bank exynos4210_pin_banks2[] = {
|
|
EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"),
|
|
};
|
|
|
|
/*
|
|
* Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
|
|
* three gpio/pin-mux/pinconfig controllers.
|
|
*/
|
|
struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
|
|
{
|
|
/* pin-controller instance 0 data */
|
|
.pin_banks = exynos4210_pin_banks0,
|
|
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
|
|
.base = EXYNOS4210_GPIO_A0_START,
|
|
.nr_pins = EXYNOS4210_GPIOA_NR_PINS,
|
|
.nr_gint = EXYNOS4210_GPIOA_NR_GINT,
|
|
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
|
|
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
|
|
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
|
|
.svc = EXYNOS_SVC_OFFSET,
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.label = "exynos4210-gpio-ctrl0",
|
|
}, {
|
|
/* pin-controller instance 1 data */
|
|
.pin_banks = exynos4210_pin_banks1,
|
|
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
|
|
.base = EXYNOS4210_GPIOA_NR_PINS,
|
|
.nr_pins = EXYNOS4210_GPIOB_NR_PINS,
|
|
.nr_gint = EXYNOS4210_GPIOB_NR_GINT,
|
|
.nr_wint = 32,
|
|
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
|
|
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
|
|
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
|
|
.weint_con = EXYNOS_WKUP_ECON_OFFSET,
|
|
.weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
|
|
.weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
|
|
.svc = EXYNOS_SVC_OFFSET,
|
|
.eint_gpio_init = exynos_eint_gpio_init,
|
|
.eint_wkup_init = exynos_eint_wkup_init,
|
|
.label = "exynos4210-gpio-ctrl1",
|
|
}, {
|
|
/* pin-controller instance 2 data */
|
|
.pin_banks = exynos4210_pin_banks2,
|
|
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
|
|
.base = EXYNOS4210_GPIOA_NR_PINS +
|
|
EXYNOS4210_GPIOB_NR_PINS,
|
|
.nr_pins = EXYNOS4210_GPIOC_NR_PINS,
|
|
.label = "exynos4210-gpio-ctrl2",
|
|
},
|
|
};
|