a81ab36bf5
None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. This covers everything under drivers/net except for wireless, which has been submitted separately. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
254 lines
6.4 KiB
C
254 lines
6.4 KiB
C
/*
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* Copyright (C) ST-Ericsson AB 2010
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* Author: Daniel Martensson
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* License terms: GNU General Public License (GPL) version 2.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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#include <linux/semaphore.h>
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#include <linux/workqueue.h>
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#include <linux/completion.h>
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#include <linux/list.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/debugfs.h>
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#include <net/caif/caif_spi.h>
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#ifndef CONFIG_CAIF_SPI_SYNC
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#define SPI_DATA_POS 0
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static inline int forward_to_spi_cmd(struct cfspi *cfspi)
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{
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return cfspi->rx_cpck_len;
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}
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#else
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#define SPI_DATA_POS SPI_CMD_SZ
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static inline int forward_to_spi_cmd(struct cfspi *cfspi)
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{
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return 0;
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}
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#endif
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int spi_frm_align = 2;
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/*
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* SPI padding options.
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* Warning: must be a base of 2 (& operation used) and can not be zero !
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*/
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int spi_up_head_align = 1 << 1;
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int spi_up_tail_align = 1 << 0;
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int spi_down_head_align = 1 << 2;
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int spi_down_tail_align = 1 << 1;
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#ifdef CONFIG_DEBUG_FS
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static inline void debugfs_store_prev(struct cfspi *cfspi)
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{
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/* Store previous command for debugging reasons.*/
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cfspi->pcmd = cfspi->cmd;
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/* Store previous transfer. */
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cfspi->tx_ppck_len = cfspi->tx_cpck_len;
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cfspi->rx_ppck_len = cfspi->rx_cpck_len;
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}
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#else
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static inline void debugfs_store_prev(struct cfspi *cfspi)
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{
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}
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#endif
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void cfspi_xfer(struct work_struct *work)
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{
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struct cfspi *cfspi;
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u8 *ptr = NULL;
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unsigned long flags;
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int ret;
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cfspi = container_of(work, struct cfspi, work);
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/* Initialize state. */
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cfspi->cmd = SPI_CMD_EOT;
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for (;;) {
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cfspi_dbg_state(cfspi, CFSPI_STATE_WAITING);
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/* Wait for master talk or transmit event. */
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wait_event_interruptible(cfspi->wait,
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test_bit(SPI_XFER, &cfspi->state) ||
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test_bit(SPI_TERMINATE, &cfspi->state));
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if (test_bit(SPI_TERMINATE, &cfspi->state))
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return;
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#if CFSPI_DBG_PREFILL
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/* Prefill buffers for easier debugging. */
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memset(cfspi->xfer.va_tx, 0xFF, SPI_DMA_BUF_LEN);
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memset(cfspi->xfer.va_rx, 0xFF, SPI_DMA_BUF_LEN);
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#endif /* CFSPI_DBG_PREFILL */
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cfspi_dbg_state(cfspi, CFSPI_STATE_AWAKE);
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/* Check whether we have a committed frame. */
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if (cfspi->tx_cpck_len) {
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int len;
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cfspi_dbg_state(cfspi, CFSPI_STATE_FETCH_PKT);
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/* Copy committed SPI frames after the SPI indication. */
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ptr = (u8 *) cfspi->xfer.va_tx;
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ptr += SPI_IND_SZ;
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len = cfspi_xmitfrm(cfspi, ptr, cfspi->tx_cpck_len);
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WARN_ON(len != cfspi->tx_cpck_len);
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}
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cfspi_dbg_state(cfspi, CFSPI_STATE_GET_NEXT);
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/* Get length of next frame to commit. */
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cfspi->tx_npck_len = cfspi_xmitlen(cfspi);
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WARN_ON(cfspi->tx_npck_len > SPI_DMA_BUF_LEN);
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/*
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* Add indication and length at the beginning of the frame,
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* using little endian.
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*/
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ptr = (u8 *) cfspi->xfer.va_tx;
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*ptr++ = SPI_CMD_IND;
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*ptr++ = (SPI_CMD_IND & 0xFF00) >> 8;
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*ptr++ = cfspi->tx_npck_len & 0x00FF;
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*ptr++ = (cfspi->tx_npck_len & 0xFF00) >> 8;
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/* Calculate length of DMAs. */
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cfspi->xfer.tx_dma_len = cfspi->tx_cpck_len + SPI_IND_SZ;
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cfspi->xfer.rx_dma_len = cfspi->rx_cpck_len + SPI_CMD_SZ;
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/* Add SPI TX frame alignment padding, if necessary. */
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if (cfspi->tx_cpck_len &&
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(cfspi->xfer.tx_dma_len % spi_frm_align)) {
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cfspi->xfer.tx_dma_len += spi_frm_align -
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(cfspi->xfer.tx_dma_len % spi_frm_align);
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}
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/* Add SPI RX frame alignment padding, if necessary. */
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if (cfspi->rx_cpck_len &&
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(cfspi->xfer.rx_dma_len % spi_frm_align)) {
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cfspi->xfer.rx_dma_len += spi_frm_align -
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(cfspi->xfer.rx_dma_len % spi_frm_align);
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}
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cfspi_dbg_state(cfspi, CFSPI_STATE_INIT_XFER);
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/* Start transfer. */
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ret = cfspi->dev->init_xfer(&cfspi->xfer, cfspi->dev);
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WARN_ON(ret);
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cfspi_dbg_state(cfspi, CFSPI_STATE_WAIT_ACTIVE);
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/*
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* TODO: We might be able to make an assumption if this is the
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* first loop. Make sure that minimum toggle time is respected.
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*/
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udelay(MIN_TRANSITION_TIME_USEC);
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cfspi_dbg_state(cfspi, CFSPI_STATE_SIG_ACTIVE);
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/* Signal that we are ready to receive data. */
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cfspi->dev->sig_xfer(true, cfspi->dev);
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cfspi_dbg_state(cfspi, CFSPI_STATE_WAIT_XFER_DONE);
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/* Wait for transfer completion. */
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wait_for_completion(&cfspi->comp);
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cfspi_dbg_state(cfspi, CFSPI_STATE_XFER_DONE);
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if (cfspi->cmd == SPI_CMD_EOT) {
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/*
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* Clear the master talk bit. A xfer is always at
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* least two bursts.
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*/
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clear_bit(SPI_SS_ON, &cfspi->state);
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}
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cfspi_dbg_state(cfspi, CFSPI_STATE_WAIT_INACTIVE);
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/* Make sure that the minimum toggle time is respected. */
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if (SPI_XFER_TIME_USEC(cfspi->xfer.tx_dma_len,
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cfspi->dev->clk_mhz) <
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MIN_TRANSITION_TIME_USEC) {
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udelay(MIN_TRANSITION_TIME_USEC -
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SPI_XFER_TIME_USEC
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(cfspi->xfer.tx_dma_len, cfspi->dev->clk_mhz));
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}
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cfspi_dbg_state(cfspi, CFSPI_STATE_SIG_INACTIVE);
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/* De-assert transfer signal. */
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cfspi->dev->sig_xfer(false, cfspi->dev);
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/* Check whether we received a CAIF packet. */
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if (cfspi->rx_cpck_len) {
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int len;
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cfspi_dbg_state(cfspi, CFSPI_STATE_DELIVER_PKT);
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/* Parse SPI frame. */
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ptr = ((u8 *)(cfspi->xfer.va_rx + SPI_DATA_POS));
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len = cfspi_rxfrm(cfspi, ptr, cfspi->rx_cpck_len);
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WARN_ON(len != cfspi->rx_cpck_len);
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}
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/* Check the next SPI command and length. */
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ptr = (u8 *) cfspi->xfer.va_rx;
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ptr += forward_to_spi_cmd(cfspi);
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cfspi->cmd = *ptr++;
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cfspi->cmd |= ((*ptr++) << 8) & 0xFF00;
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cfspi->rx_npck_len = *ptr++;
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cfspi->rx_npck_len |= ((*ptr++) << 8) & 0xFF00;
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WARN_ON(cfspi->rx_npck_len > SPI_DMA_BUF_LEN);
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WARN_ON(cfspi->cmd > SPI_CMD_EOT);
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debugfs_store_prev(cfspi);
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/* Check whether the master issued an EOT command. */
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if (cfspi->cmd == SPI_CMD_EOT) {
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/* Reset state. */
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cfspi->tx_cpck_len = 0;
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cfspi->rx_cpck_len = 0;
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} else {
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/* Update state. */
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cfspi->tx_cpck_len = cfspi->tx_npck_len;
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cfspi->rx_cpck_len = cfspi->rx_npck_len;
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}
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/*
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* Check whether we need to clear the xfer bit.
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* Spin lock needed for packet insertion.
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* Test and clear of different bits
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* are not supported.
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*/
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spin_lock_irqsave(&cfspi->lock, flags);
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if (cfspi->cmd == SPI_CMD_EOT && !cfspi_xmitlen(cfspi)
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&& !test_bit(SPI_SS_ON, &cfspi->state))
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clear_bit(SPI_XFER, &cfspi->state);
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spin_unlock_irqrestore(&cfspi->lock, flags);
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}
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}
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struct platform_driver cfspi_spi_driver = {
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.probe = cfspi_spi_probe,
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.remove = cfspi_spi_remove,
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.driver = {
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.name = "cfspi_sspi",
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.owner = THIS_MODULE,
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},
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};
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