9904f22a72
This adds a bitbanging spi master, hooking up to board/adapter-specific glue code which knows how to set and read the signals (gpios etc). This code kicks in after the glue code creates a platform_device with the right platform_data. That data includes I/O loops, which will usually come from expanding an inline function (provided in the header). One goal is that the I/O loops should be easily optimized down to a few GPIO register accesses, in common cases, for speed and minimized overhead. This understands all the currently defined protocol tweaking options in the SPI framework, and might eventually serve as as reference implementation. - different word sizes (1..32 bits) - differing clock rates - SPI modes differing by CPOL (affecting chip select and I/O loops) - SPI modes differing by CPHA (affecting I/O loops) - delays (usecs) after transfers - temporarily deselecting chips in mid-transfer A lot of hardware could work with this framework, though common types of controller can't reach peak performance without switching to a driver structure that supports pipelining of transfers (e.g. DMA queues) and maybe controllers (e.g. IRQ driven). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| spi.c | ||
| spi_bitbang.c | ||