20780fcc40
This patch adds support HRT for machines of S5P64X0 and S5PV210. Basically, PWM Timer3 is used for clockevent and PWM Timer4 is used for clocksource. Since PWM Timer3 is used for other purpose, PWM Timer2 is used on SMDKV210. Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
133 lines
3.3 KiB
C
133 lines
3.3 KiB
C
/* linux/arch/arm/mach-s5pv210/mach-torbreck.c
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*
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* Copyright (c) 2010 aESOP Community
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* http://www.aesop.or.kr/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/regs-serial.h>
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#include <plat/s5pv210.h>
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#include <plat/devs.h>
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#include <plat/cpu.h>
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#include <plat/iic.h>
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#include <plat/s5p-time.h>
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/* Following are default values for UCON, ULCON and UFCON UART registers */
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#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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S3C2410_UCON_RXILEVEL | \
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S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI | \
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S3C2443_UCON_RXERR_IRQEN)
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#define TORBRECK_ULCON_DEFAULT S3C2410_LCON_CS8
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#define TORBRECK_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
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S5PV210_UFCON_TXTRIG4 | \
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S5PV210_UFCON_RXTRIG4)
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static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = TORBRECK_UCON_DEFAULT,
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.ulcon = TORBRECK_ULCON_DEFAULT,
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.ufcon = TORBRECK_UFCON_DEFAULT,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = TORBRECK_UCON_DEFAULT,
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.ulcon = TORBRECK_ULCON_DEFAULT,
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.ufcon = TORBRECK_UFCON_DEFAULT,
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = TORBRECK_UCON_DEFAULT,
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.ulcon = TORBRECK_ULCON_DEFAULT,
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.ufcon = TORBRECK_UFCON_DEFAULT,
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},
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[3] = {
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.hwport = 3,
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.flags = 0,
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.ucon = TORBRECK_UCON_DEFAULT,
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.ulcon = TORBRECK_ULCON_DEFAULT,
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.ufcon = TORBRECK_UFCON_DEFAULT,
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},
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};
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static struct platform_device *torbreck_devices[] __initdata = {
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&s5pv210_device_iis0,
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&s3c_device_cfcon,
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&s3c_device_hsmmc0,
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&s3c_device_hsmmc1,
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&s3c_device_hsmmc2,
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&s3c_device_hsmmc3,
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&s3c_device_i2c0,
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&s3c_device_i2c1,
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&s3c_device_i2c2,
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&s3c_device_rtc,
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&s3c_device_wdt,
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};
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static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
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/* To Be Updated */
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};
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static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
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/* To Be Updated */
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};
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static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
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/* To Be Updated */
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};
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static void __init torbreck_map_io(void)
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{
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s5p_init_io(NULL, 0, S5P_VA_CHIPID);
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s3c24xx_init_clocks(24000000);
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s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
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s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
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}
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static void __init torbreck_machine_init(void)
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{
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s3c_i2c0_set_platdata(NULL);
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s3c_i2c1_set_platdata(NULL);
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s3c_i2c2_set_platdata(NULL);
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i2c_register_board_info(0, torbreck_i2c_devs0,
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ARRAY_SIZE(torbreck_i2c_devs0));
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i2c_register_board_info(1, torbreck_i2c_devs1,
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ARRAY_SIZE(torbreck_i2c_devs1));
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i2c_register_board_info(2, torbreck_i2c_devs2,
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ARRAY_SIZE(torbreck_i2c_devs2));
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platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
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}
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MACHINE_START(TORBRECK, "TORBRECK")
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/* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
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.boot_params = S5P_PA_SDRAM + 0x100,
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.init_irq = s5pv210_init_irq,
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.map_io = torbreck_map_io,
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.init_machine = torbreck_machine_init,
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.timer = &s5p_timer,
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MACHINE_END
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