5aa85c9fc4
The R4000 and R4400 have an errata where if the cp0 count register is read in the exact moment when it matches the compare register no interrupt will be generated. This bug may be triggered if the cp0 count register is being used as clocksource and the compare interrupt as clockevent. So a simple workaround is to avoid using the compare for both facilities on the affected CPUs. This is different from the workaround suggested in the old errata documents; at some opportunity probably the official version should be implemented and tested. Another thing to find out is which processor versions exactly are affected. I only have errata documents upto R4400 V3.0 available so for the moment the code treats all R4000 and R4400 as broken. This is potencially a problem for some machines that have no other decent clocksource available; this workaround will cause them to fall back to another clocksource, worst case the "jiffies" source.
292 lines
6.7 KiB
C
292 lines
6.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 MIPS Technologies, Inc.
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* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <asm/smtc_ipi.h>
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#include <asm/time.h>
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned int cnt;
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int res;
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#ifdef CONFIG_MIPS_MT_SMTC
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{
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unsigned long flags, vpflags;
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local_irq_save(flags);
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vpflags = dvpe();
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#endif
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
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#ifdef CONFIG_MIPS_MT_SMTC
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evpe(vpflags);
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local_irq_restore(flags);
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}
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#endif
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return res;
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}
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static void mips_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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/* Nothing to do ... */
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}
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static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
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static int cp0_timer_irq_installed;
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/*
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* Timer ack for an R4k-compatible timer of a known frequency.
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*/
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static void c0_timer_ack(void)
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{
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write_c0_compare(read_c0_compare());
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}
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/*
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* Possibly handle a performance counter interrupt.
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* Return true if the timer interrupt should not be checked
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*/
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static inline int handle_perf_irq(int r2)
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{
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/*
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* The performance counter overflow interrupt may be shared with the
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* timer interrupt (cp0_perfcount_irq < 0). If it is and a
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* performance counter has overflowed (perf_irq() == IRQ_HANDLED)
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* and we can't reliably determine if a counter interrupt has also
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* happened (!r2) then don't check for a timer interrupt.
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*/
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return (cp0_perfcount_irq < 0) &&
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perf_irq() == IRQ_HANDLED &&
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!r2;
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}
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static irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
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{
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const int r2 = cpu_has_mips_r2;
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struct clock_event_device *cd;
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int cpu = smp_processor_id();
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/*
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* Suckage alert:
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* Before R2 of the architecture there was no way to see if a
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* performance counter interrupt was pending, so we have to run
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* the performance counter interrupt handler anyway.
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*/
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if (handle_perf_irq(r2))
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goto out;
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/*
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* The same applies to performance counter interrupts. But with the
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* above we now know that the reason we got here must be a timer
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* interrupt. Being the paranoiacs we are we check anyway.
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*/
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if (!r2 || (read_c0_cause() & (1 << 30))) {
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c0_timer_ack();
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#ifdef CONFIG_MIPS_MT_SMTC
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if (cpu_data[cpu].vpe_id)
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goto out;
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cpu = 0;
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#endif
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->event_handler(cd);
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}
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out:
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return IRQ_HANDLED;
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}
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static struct irqaction c0_compare_irqaction = {
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.handler = c0_compare_interrupt,
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#ifdef CONFIG_MIPS_MT_SMTC
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.flags = IRQF_DISABLED,
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#else
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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#endif
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.name = "timer",
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};
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#ifdef CONFIG_MIPS_MT_SMTC
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DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
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static void smtc_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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}
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static void mips_broadcast(cpumask_t mask)
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{
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unsigned int cpu;
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for_each_cpu_mask(cpu, mask)
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smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
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}
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static void setup_smtc_dummy_clockevent_device(void)
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{
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//uint64_t mips_freq = mips_hpt_^frequency;
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
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cd->name = "SMTC";
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cd->features = CLOCK_EVT_FEAT_DUMMY;
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/* Calculate the min / max delta */
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cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
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cd->shift = 0; //32;
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cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd);
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cd->rating = 200;
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cd->irq = 17; //-1;
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// if (cpu)
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// cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
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// else
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cd->cpumask = cpumask_of_cpu(cpu);
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cd->set_mode = smtc_set_mode;
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cd->broadcast = mips_broadcast;
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clockevents_register_device(cd);
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}
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#endif
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static void mips_event_handler(struct clock_event_device *dev)
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{
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}
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/*
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* FIXME: This doesn't hold for the relocated E9000 compare interrupt.
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*/
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static int c0_compare_int_pending(void)
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{
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return (read_c0_cause() >> cp0_compare_irq) & 0x100;
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}
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static int c0_compare_int_usable(void)
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{
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unsigned int delta;
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unsigned int cnt;
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/*
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* IP7 already pending? Try to clear it by acking the timer.
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*/
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if (c0_compare_int_pending()) {
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write_c0_compare(read_c0_count());
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irq_disable_hazard();
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if (c0_compare_int_pending())
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return 0;
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}
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for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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irq_disable_hazard();
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if ((int)(read_c0_count() - cnt) < 0)
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break;
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/* increase delta if the timer was already expired */
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}
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while ((int)(read_c0_count() - cnt) <= 0)
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; /* Wait for expiry */
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if (!c0_compare_int_pending())
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return 0;
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write_c0_compare(read_c0_count());
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irq_disable_hazard();
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if (c0_compare_int_pending())
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return 0;
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/*
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* Feels like a real count / compare timer.
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*/
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return 1;
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}
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int __cpuinit mips_clockevent_init(void)
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{
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uint64_t mips_freq = mips_hpt_frequency;
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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unsigned int irq;
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if (!cpu_has_counter || !mips_hpt_frequency)
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return -ENXIO;
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_smtc_dummy_clockevent_device();
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/*
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* On SMTC we only register VPE0's compare interrupt as clockevent
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* device.
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*/
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if (cpu)
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return 0;
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#endif
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if (!c0_compare_int_usable())
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return -ENXIO;
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/*
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* With vectored interrupts things are getting platform specific.
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* get_c0_compare_int is a hook to allow a platform to return the
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* interrupt number of it's liking.
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*/
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irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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if (get_c0_compare_int)
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irq = get_c0_compare_int();
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->name = "MIPS";
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cd->features = CLOCK_EVT_FEAT_ONESHOT;
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/* Calculate the min / max delta */
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cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
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cd->shift = 32;
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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cd->rating = 300;
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cd->irq = irq;
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#ifdef CONFIG_MIPS_MT_SMTC
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cd->cpumask = CPU_MASK_ALL;
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#else
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cd->cpumask = cpumask_of_cpu(cpu);
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#endif
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cd->set_next_event = mips_next_event;
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cd->set_mode = mips_set_mode;
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cd->event_handler = mips_event_handler;
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clockevents_register_device(cd);
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if (cp0_timer_irq_installed)
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return 0;
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cp0_timer_irq_installed = 1;
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#ifdef CONFIG_MIPS_MT_SMTC
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#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
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setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT);
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#else
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setup_irq(irq, &c0_compare_irqaction);
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#endif
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return 0;
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}
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