02b2944cd7
Fix the ASB2364 gdbport UART register definitions. These registers are actually 2 bytes apart, not 4 (which the ASB2303 and ASB2305 are). Signed-off-by: David Howells <dhowells@redhat.com>
151 lines
4.1 KiB
C
151 lines
4.1 KiB
C
/* Unit-specific 8250 serial ports
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*
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* Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_UNIT_SERIAL_H
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#define _ASM_UNIT_SERIAL_H
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#include <asm/cpu-regs.h>
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#include <proc/irq.h>
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#include <unit/fpga-regs.h>
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#include <linux/serial_reg.h>
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#define SERIAL_PORT0_BASE_ADDRESS 0xA8200000
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#define SERIAL_IRQ XIRQ1 /* single serial (TL16C550C) (Lo) */
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/*
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* The ASB2364 has an 12.288 MHz clock
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* for your UART.
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*
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* It'd be nice if someone built a serial card with a 24.576 MHz
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* clock, since the 16550A is capable of handling a top speed of 1.5
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* megabits/second; but this requires the faster clock.
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*/
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#define BASE_BAUD (12288000 / 16)
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/*
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* dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports
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*/
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#ifndef CONFIG_GDBSTUB_ON_TTYSx
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#define SERIAL_PORT_DFNS \
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{ \
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.baud_base = BASE_BAUD, \
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.irq = SERIAL_IRQ, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \
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.iomem_reg_shift = 1, \
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.io_type = SERIAL_IO_MEM, \
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},
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#ifndef __ASSEMBLY__
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static inline void __debug_to_serial(const char *p, int n)
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{
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}
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#endif /* !__ASSEMBLY__ */
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#else /* CONFIG_GDBSTUB_ON_TTYSx */
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#define SERIAL_PORT_DFNS /* stolen by gdb-stub */
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#if defined(CONFIG_GDBSTUB_ON_TTYS0)
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#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 2, u8)
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#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 2, u8)
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#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 2, u8)
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#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 2, u8)
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#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8)
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#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 2, u8)
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#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 2, u8)
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#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 2, u8)
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#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 2, u8)
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#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 2, u8)
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#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 2, u8)
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#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 2, u8)
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#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
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#elif defined(CONFIG_GDBSTUB_ON_TTYS1)
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#error The ASB2364 does not have a /dev/ttyS1
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#endif
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#ifndef __ASSEMBLY__
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static inline void __debug_to_serial(const char *p, int n)
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{
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char ch;
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#define LSR_WAIT_FOR(STATE) \
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do {} while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE))
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#define FLOWCTL_QUERY(LINE) \
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({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; })
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#define FLOWCTL_WAIT_FOR(LINE) \
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do {} while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE))
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#define FLOWCTL_CLEAR(LINE) \
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do { GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; } while (0)
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#define FLOWCTL_SET(LINE) \
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do { GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; } while (0)
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FLOWCTL_SET(DTR);
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for (; n > 0; n--) {
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LSR_WAIT_FOR(THRE);
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FLOWCTL_WAIT_FOR(CTS);
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ch = *p++;
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if (ch == 0x0a) {
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GDBPORT_SERIAL_TX = 0x0d;
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LSR_WAIT_FOR(THRE);
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FLOWCTL_WAIT_FOR(CTS);
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}
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GDBPORT_SERIAL_TX = ch;
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}
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FLOWCTL_CLEAR(DTR);
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* CONFIG_GDBSTUB_ON_TTYSx */
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#define SERIAL_INITIALIZE \
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do { \
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/* release reset */ \
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ASB2364_FPGA_REG_RESET_UART = 0x0001; \
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SyncExBus(); \
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} while (0)
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#define SERIAL_CHECK_INTERRUPT \
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do { \
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if ((ASB2364_FPGA_REG_IRQ_UART & 0x0001) == 0x0001) { \
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return IRQ_NONE; \
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} \
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} while (0)
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#define SERIAL_CLEAR_INTERRUPT \
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do { \
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ASB2364_FPGA_REG_IRQ_UART = 0x0001; \
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SyncExBus(); \
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} while (0)
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#define SERIAL_SET_INT_MASK \
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do { \
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ASB2364_FPGA_REG_MASK_UART = 0x0001; \
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SyncExBus(); \
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} while (0)
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#define SERIAL_CLEAR_INT_MASK \
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do { \
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ASB2364_FPGA_REG_MASK_UART = 0x0000; \
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SyncExBus(); \
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} while (0)
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#endif /* _ASM_UNIT_SERIAL_H */
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