97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
78 lines
3.1 KiB
C
78 lines
3.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* ip22.h: Definitions for SGI IP22 machines
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*
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* Copyright (C) 1996 David S. Miller
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* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
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*/
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#ifndef _SGI_IP22_H
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#define _SGI_IP22_H
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/*
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* These are the virtual IRQ numbers, we divide all IRQ's into
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* 'spaces', the 'space' determines where and how to enable/disable
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* that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
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* are not supported this way. Driver is supposed to allocate HPC/MC
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* interrupt as shareable and then look to proper status bit (see
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* HAL2 driver). This will prevent many complications, trust me ;-)
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*/
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#include <irq.h>
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#include <asm/sgi/ioc.h>
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#define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */
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#define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
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#define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */
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#define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */
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#define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */
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#define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */
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#define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */
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/*
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* Individual interrupt definitions for the Indy and Indigo2
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*/
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#define SGI_SOFT_0_IRQ SGINT_CPU + 0
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#define SGI_SOFT_1_IRQ SGINT_CPU + 1
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#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
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#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
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#define SGI_8254_0_IRQ SGINT_CPU + 4
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#define SGI_8254_1_IRQ SGINT_CPU + 5
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#define SGI_BUSERR_IRQ SGINT_CPU + 6
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#define SGI_TIMER_IRQ SGINT_CPU + 7
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#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */
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#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */
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#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
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#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
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#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
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#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */
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#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */
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#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */
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#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */
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#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */
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#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
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#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */
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#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */
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#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */
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#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */
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#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */
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#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */
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/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
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#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */
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#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
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#define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */
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#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
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#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
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extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg);
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extern unsigned short ip22_nvram_read(int reg);
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#endif
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