4e6d488af3
Otherwise more complicated uart configuration won't be possible. We can use r1 for tmp register for both head.S and debug.S. NOTE: This patch depends on another patch to add the the tmp register into all debug-macro.S files. That can be done with: $ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/" arch/arm/*/include/*/debug-macro.S Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
102 lines
2.8 KiB
ArmAsm
102 lines
2.8 KiB
ArmAsm
/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Copyright (C) 2005 Simtec Electronics
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*
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <mach/map.h>
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#include <mach/regs-gpio.h>
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#include <plat/regs-serial.h>
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#define S3C2410_UART1_OFF (0x4000)
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#define SHIFT_2440TXF (14-9)
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.macro addruart, rx, tmp
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mrc p15, 0, \rx, c1, c0
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tst \rx, #1
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ldreq \rx, = S3C24XX_PA_UART
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ldrne \rx, = S3C24XX_VA_UART
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#if CONFIG_DEBUG_S3C_UART != 0
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add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
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#endif
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.endm
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.macro fifo_full_s3c24xx rd, rx
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@ check for arm920 vs arm926. currently assume all arm926
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@ devices have an 64 byte FIFO identical to the s3c2440
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mrc p15, 0, \rd, c0, c0
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and \rd, \rd, #0xff0
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teq \rd, #0x260
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beq 1004f
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mrc p15, 0, \rd, c1, c0
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tst \rd, #1
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addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
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addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
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bic \rd, \rd, #0xff000
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ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
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and \rd, \rd, #0x00ff0000
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teq \rd, #0x00440000 @ is it 2440?
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1004:
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ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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moveq \rd, \rd, lsr #SHIFT_2440TXF
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tst \rd, #S3C2410_UFSTAT_TXFULL
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.endm
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.macro fifo_full_s3c2410 rd, rx
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ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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tst \rd, #S3C2410_UFSTAT_TXFULL
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.endm
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/* fifo level reading */
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.macro fifo_level_s3c24xx rd, rx
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@ check for arm920 vs arm926. currently assume all arm926
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@ devices have an 64 byte FIFO identical to the s3c2440
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mrc p15, 0, \rd, c0, c0
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and \rd, \rd, #0xff0
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teq \rd, #0x260
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beq 10000f
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mrc p15, 0, \rd, c1, c0
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tst \rd, #1
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addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
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addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
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bic \rd, \rd, #0xff000
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ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
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and \rd, \rd, #0x00ff0000
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teq \rd, #0x00440000 @ is it 2440?
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10000:
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ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
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andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
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.endm
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.macro fifo_level_s3c2410 rd, rx
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ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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and \rd, \rd, #S3C2410_UFSTAT_TXMASK
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.endm
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/* Select the correct implementation depending on the configuration. The
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* S3C2440 will get selected by default, as these are the most widely
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* used variants of these
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*/
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#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
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#define fifo_full fifo_full_s3c2410
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#define fifo_level fifo_level_s3c2410
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#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
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#define fifo_full fifo_full_s3c24xx
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#define fifo_level fifo_level_s3c24xx
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#endif
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/* include the reset of the code which will do the work */
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#include <plat/debug-macro.S>
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