9524705c86
i.MX35 CPUs marked with "MCIMX357CJQ5C M99V CTHA0943B" are coming with bogus L2 cache settings. If these settings are kept unmodified prior enabling the L2 cache the CPU runs amok immediately when its enabled. This fix should not hurt already working CPUs, as they are using the written register value already. Its currently unknown if its possible to detect the production lot from the software to fix only affected CPUs. While at it, make sure that mxc_init_l2x0 is only executed on i.MX31/35 Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
146 lines
3.8 KiB
C
146 lines
3.8 KiB
C
/*
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* Copyright (C) 1999,2000 Arm Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* - add MX31 specific definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <mach/iomux-v3.h>
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/*!
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* @file mm.c
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*
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* @brief This file creates static virtual to physical mappings, common to all MX3 boards.
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*
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* @ingroup Memory
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*/
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/*!
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* This table defines static virtual address mappings for I/O regions.
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* These are the mappings common across all MX3 boards.
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*/
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static struct map_desc mxc_io_desc[] __initdata = {
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{
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.virtual = X_MEMC_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
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.length = X_MEMC_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = AVIC_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(AVIC_BASE_ADDR),
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.length = AVIC_SIZE,
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.type = MT_DEVICE_NONSHARED
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}, {
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.virtual = AIPS1_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
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.length = AIPS1_SIZE,
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.type = MT_DEVICE_NONSHARED
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}, {
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.virtual = AIPS2_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
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.length = AIPS2_SIZE,
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.type = MT_DEVICE_NONSHARED
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}, {
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.virtual = SPBA0_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
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.length = SPBA0_SIZE,
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.type = MT_DEVICE_NONSHARED
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},
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};
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/*!
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* This function initializes the memory map. It is called during the
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* system startup to create static physical to virtual memory mappings
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* for the IO modules.
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*/
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void __init mx31_map_io(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX31);
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mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
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iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
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}
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#ifdef CONFIG_ARCH_MX35
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void __init mx35_map_io(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX35);
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mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
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iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
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}
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#endif
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int imx3x_register_gpios(void);
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void __init mx31_init_irq(void)
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{
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mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
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imx3x_register_gpios();
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}
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void __init mx35_init_irq(void)
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{
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mx31_init_irq();
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}
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#ifdef CONFIG_CACHE_L2X0
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static int mxc_init_l2x0(void)
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{
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void __iomem *l2x0_base;
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void __iomem *clkctl_base;
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/*
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* First of all, we must repair broken chip settings. There are some
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* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
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* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
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* Workaraound is to setup the correct register setting prior enabling the
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* L2 cache. This should not hurt already working CPUs, as they are using the
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* same value
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*/
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#define L2_MEM_VAL 0x10
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clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
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if (clkctl_base != NULL) {
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writel(0x00000515, clkctl_base + L2_MEM_VAL);
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iounmap(clkctl_base);
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} else {
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pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
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}
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l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
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if (IS_ERR(l2x0_base)) {
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printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
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PTR_ERR(l2x0_base));
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return 0;
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}
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l2x0_init(l2x0_base, 0x00030024, 0x00000000);
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return 0;
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}
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arch_initcall(mxc_init_l2x0);
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#endif
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