f5c4227133
This patch does the actual device tree switch for the LPC32xx SoC. Signed-off-by: Roland Stigge <stigge@antcom.de>
38 lines
1.1 KiB
Text
38 lines
1.1 KiB
Text
* NXP LPC32xx Main Interrupt Controller
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(MIC, including SIC1 and SIC2 secondary controllers)
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Required properties:
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- compatible: Should be "nxp,lpc3220-mic"
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- interrupt-controller: Identifies the node as an interrupt controller.
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- interrupt-parent: Empty for the interrupt controller itself
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- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
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The first cell is the IRQ number
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The second cell is used to specify mode:
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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Default for internal sources should be set to 4 (active high).
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- reg: Should contain MIC registers location and length
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Examples:
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/*
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* MIC
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*/
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mic: interrupt-controller@40008000 {
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compatible = "nxp,lpc3220-mic";
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interrupt-controller;
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interrupt-parent;
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#interrupt-cells = <2>;
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reg = <0x40008000 0xC000>;
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};
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/*
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* ADC
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*/
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adc@40048000 {
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compatible = "nxp,lpc3220-adc";
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reg = <0x40048000 0x1000>;
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interrupt-parent = <&mic>;
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interrupts = <39 4>;
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};
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