5a0e3ad6af
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
538 lines
13 KiB
C
538 lines
13 KiB
C
/*
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* Platform dependent support for SGI SN
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2000-2008 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/rculist.h>
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#include <linux/slab.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/arch.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/shub_mmr.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/sn_feature_sets.h>
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static void force_interrupt(int irq);
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static void register_intr_pda(struct sn_irq_info *sn_irq_info);
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static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
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int sn_force_interrupt_flag = 1;
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extern int sn_ioif_inited;
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struct list_head **sn_irq_lh;
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static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
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u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
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struct sn_irq_info *sn_irq_info,
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int req_irq, nasid_t req_nasid,
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int req_slice)
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{
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struct ia64_sal_retval ret_stuff;
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ret_stuff.status = 0;
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ret_stuff.v0 = 0;
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SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
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(u64) SAL_INTR_ALLOC, (u64) local_nasid,
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(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
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(u64) req_nasid, (u64) req_slice);
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return ret_stuff.status;
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}
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void sn_intr_free(nasid_t local_nasid, int local_widget,
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struct sn_irq_info *sn_irq_info)
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{
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struct ia64_sal_retval ret_stuff;
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ret_stuff.status = 0;
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ret_stuff.v0 = 0;
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SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
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(u64) SAL_INTR_FREE, (u64) local_nasid,
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(u64) local_widget, (u64) sn_irq_info->irq_irq,
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(u64) sn_irq_info->irq_cookie, 0, 0);
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}
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u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
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struct sn_irq_info *sn_irq_info,
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nasid_t req_nasid, int req_slice)
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{
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struct ia64_sal_retval ret_stuff;
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ret_stuff.status = 0;
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ret_stuff.v0 = 0;
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SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
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(u64) SAL_INTR_REDIRECT, (u64) local_nasid,
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(u64) local_widget, __pa(sn_irq_info),
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(u64) req_nasid, (u64) req_slice, 0);
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return ret_stuff.status;
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}
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static unsigned int sn_startup_irq(unsigned int irq)
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{
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return 0;
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}
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static void sn_shutdown_irq(unsigned int irq)
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{
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}
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extern void ia64_mca_register_cpev(int);
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static void sn_disable_irq(unsigned int irq)
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{
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if (irq == local_vector_to_irq(IA64_CPE_VECTOR))
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ia64_mca_register_cpev(0);
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}
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static void sn_enable_irq(unsigned int irq)
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{
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if (irq == local_vector_to_irq(IA64_CPE_VECTOR))
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ia64_mca_register_cpev(irq);
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}
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static void sn_ack_irq(unsigned int irq)
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{
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u64 event_occurred, mask;
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irq = irq & 0xff;
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event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
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mask = event_occurred & SH_ALL_INT_MASK;
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HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
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__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
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move_native_irq(irq);
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}
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static void sn_end_irq(unsigned int irq)
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{
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int ivec;
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u64 event_occurred;
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ivec = irq & 0xff;
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if (ivec == SGI_UART_VECTOR) {
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event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
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/* If the UART bit is set here, we may have received an
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* interrupt from the UART that the driver missed. To
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* make sure, we IPI ourselves to force us to look again.
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*/
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if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
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platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
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IA64_IPI_DM_INT, 0);
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}
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}
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__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
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if (sn_force_interrupt_flag)
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force_interrupt(irq);
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}
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static void sn_irq_info_free(struct rcu_head *head);
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struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
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nasid_t nasid, int slice)
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{
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int vector;
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int cpuid;
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#ifdef CONFIG_SMP
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int cpuphys;
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#endif
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int64_t bridge;
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int local_widget, status;
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nasid_t local_nasid;
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struct sn_irq_info *new_irq_info;
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struct sn_pcibus_provider *pci_provider;
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bridge = (u64) sn_irq_info->irq_bridge;
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if (!bridge) {
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return NULL; /* irq is not a device interrupt */
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}
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local_nasid = NASID_GET(bridge);
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if (local_nasid & 1)
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local_widget = TIO_SWIN_WIDGETNUM(bridge);
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else
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local_widget = SWIN_WIDGETNUM(bridge);
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vector = sn_irq_info->irq_irq;
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/* Make use of SAL_INTR_REDIRECT if PROM supports it */
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status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice);
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if (!status) {
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new_irq_info = sn_irq_info;
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goto finish_up;
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}
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/*
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* PROM does not support SAL_INTR_REDIRECT, or it failed.
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* Revert to old method.
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*/
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new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
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if (new_irq_info == NULL)
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return NULL;
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memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
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/* Free the old PROM new_irq_info structure */
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sn_intr_free(local_nasid, local_widget, new_irq_info);
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unregister_intr_pda(new_irq_info);
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/* allocate a new PROM new_irq_info struct */
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status = sn_intr_alloc(local_nasid, local_widget,
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new_irq_info, vector,
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nasid, slice);
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/* SAL call failed */
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if (status) {
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kfree(new_irq_info);
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return NULL;
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}
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register_intr_pda(new_irq_info);
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spin_lock(&sn_irq_info_lock);
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list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
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spin_unlock(&sn_irq_info_lock);
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call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
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finish_up:
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/* Update kernels new_irq_info with new target info */
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cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
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new_irq_info->irq_slice);
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new_irq_info->irq_cpuid = cpuid;
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pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
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/*
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* If this represents a line interrupt, target it. If it's
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* an msi (irq_int_bit < 0), it's already targeted.
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*/
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if (new_irq_info->irq_int_bit >= 0 &&
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pci_provider && pci_provider->target_interrupt)
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(pci_provider->target_interrupt)(new_irq_info);
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#ifdef CONFIG_SMP
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cpuphys = cpu_physical_id(cpuid);
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set_irq_affinity_info((vector & 0xff), cpuphys, 0);
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#endif
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return new_irq_info;
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}
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static int sn_set_affinity_irq(unsigned int irq, const struct cpumask *mask)
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{
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struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
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nasid_t nasid;
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int slice;
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nasid = cpuid_to_nasid(cpumask_first(mask));
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slice = cpuid_to_slice(cpumask_first(mask));
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list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
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sn_irq_lh[irq], list)
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(void)sn_retarget_vector(sn_irq_info, nasid, slice);
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return 0;
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}
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#ifdef CONFIG_SMP
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void sn_set_err_irq_affinity(unsigned int irq)
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{
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/*
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* On systems which support CPU disabling (SHub2), all error interrupts
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* are targetted at the boot CPU.
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*/
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if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT))
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set_irq_affinity_info(irq, cpu_physical_id(0), 0);
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}
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#else
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void sn_set_err_irq_affinity(unsigned int irq) { }
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#endif
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static void
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sn_mask_irq(unsigned int irq)
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{
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}
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static void
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sn_unmask_irq(unsigned int irq)
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{
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}
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struct irq_chip irq_type_sn = {
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.name = "SN hub",
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.startup = sn_startup_irq,
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.shutdown = sn_shutdown_irq,
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.enable = sn_enable_irq,
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.disable = sn_disable_irq,
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.ack = sn_ack_irq,
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.end = sn_end_irq,
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.mask = sn_mask_irq,
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.unmask = sn_unmask_irq,
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.set_affinity = sn_set_affinity_irq
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};
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ia64_vector sn_irq_to_vector(int irq)
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{
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if (irq >= IA64_NUM_VECTORS)
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return 0;
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return (ia64_vector)irq;
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}
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unsigned int sn_local_vector_to_irq(u8 vector)
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{
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return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
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}
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void sn_irq_init(void)
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{
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int i;
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struct irq_desc *base_desc = irq_desc;
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ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
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ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
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for (i = 0; i < NR_IRQS; i++) {
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if (base_desc[i].chip == &no_irq_chip) {
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base_desc[i].chip = &irq_type_sn;
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}
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}
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}
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static void register_intr_pda(struct sn_irq_info *sn_irq_info)
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{
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int irq = sn_irq_info->irq_irq;
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int cpu = sn_irq_info->irq_cpuid;
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if (pdacpu(cpu)->sn_last_irq < irq) {
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pdacpu(cpu)->sn_last_irq = irq;
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}
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if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
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pdacpu(cpu)->sn_first_irq = irq;
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}
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static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
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{
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int irq = sn_irq_info->irq_irq;
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int cpu = sn_irq_info->irq_cpuid;
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struct sn_irq_info *tmp_irq_info;
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int i, foundmatch;
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rcu_read_lock();
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if (pdacpu(cpu)->sn_last_irq == irq) {
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foundmatch = 0;
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for (i = pdacpu(cpu)->sn_last_irq - 1;
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i && !foundmatch; i--) {
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list_for_each_entry_rcu(tmp_irq_info,
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sn_irq_lh[i],
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list) {
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if (tmp_irq_info->irq_cpuid == cpu) {
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foundmatch = 1;
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break;
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}
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}
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}
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pdacpu(cpu)->sn_last_irq = i;
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}
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if (pdacpu(cpu)->sn_first_irq == irq) {
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foundmatch = 0;
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for (i = pdacpu(cpu)->sn_first_irq + 1;
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i < NR_IRQS && !foundmatch; i++) {
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list_for_each_entry_rcu(tmp_irq_info,
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sn_irq_lh[i],
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list) {
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if (tmp_irq_info->irq_cpuid == cpu) {
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foundmatch = 1;
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break;
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}
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}
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}
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pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
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}
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rcu_read_unlock();
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}
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static void sn_irq_info_free(struct rcu_head *head)
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{
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struct sn_irq_info *sn_irq_info;
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sn_irq_info = container_of(head, struct sn_irq_info, rcu);
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kfree(sn_irq_info);
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}
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void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
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{
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nasid_t nasid = sn_irq_info->irq_nasid;
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int slice = sn_irq_info->irq_slice;
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int cpu = nasid_slice_to_cpuid(nasid, slice);
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#ifdef CONFIG_SMP
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int cpuphys;
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struct irq_desc *desc;
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#endif
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pci_dev_get(pci_dev);
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sn_irq_info->irq_cpuid = cpu;
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sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
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/* link it into the sn_irq[irq] list */
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spin_lock(&sn_irq_info_lock);
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list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
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reserve_irq_vector(sn_irq_info->irq_irq);
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spin_unlock(&sn_irq_info_lock);
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register_intr_pda(sn_irq_info);
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#ifdef CONFIG_SMP
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cpuphys = cpu_physical_id(cpu);
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set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
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desc = irq_to_desc(sn_irq_info->irq_irq);
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/*
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* Affinity was set by the PROM, prevent it from
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* being reset by the request_irq() path.
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*/
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desc->status |= IRQ_AFFINITY_SET;
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#endif
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}
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void sn_irq_unfixup(struct pci_dev *pci_dev)
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{
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struct sn_irq_info *sn_irq_info;
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/* Only cleanup IRQ stuff if this device has a host bus context */
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if (!SN_PCIDEV_BUSSOFT(pci_dev))
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return;
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sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
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if (!sn_irq_info)
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return;
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if (!sn_irq_info->irq_irq) {
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kfree(sn_irq_info);
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return;
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}
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unregister_intr_pda(sn_irq_info);
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spin_lock(&sn_irq_info_lock);
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list_del_rcu(&sn_irq_info->list);
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spin_unlock(&sn_irq_info_lock);
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if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
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free_irq_vector(sn_irq_info->irq_irq);
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call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
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pci_dev_put(pci_dev);
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}
|
|
|
|
static inline void
|
|
sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
|
|
{
|
|
struct sn_pcibus_provider *pci_provider;
|
|
|
|
pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
|
|
|
|
/* Don't force an interrupt if the irq has been disabled */
|
|
if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) &&
|
|
pci_provider && pci_provider->force_interrupt)
|
|
(*pci_provider->force_interrupt)(sn_irq_info);
|
|
}
|
|
|
|
static void force_interrupt(int irq)
|
|
{
|
|
struct sn_irq_info *sn_irq_info;
|
|
|
|
if (!sn_ioif_inited)
|
|
return;
|
|
|
|
rcu_read_lock();
|
|
list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
|
|
sn_call_force_intr_provider(sn_irq_info);
|
|
|
|
rcu_read_unlock();
|
|
}
|
|
|
|
/*
|
|
* Check for lost interrupts. If the PIC int_status reg. says that
|
|
* an interrupt has been sent, but not handled, and the interrupt
|
|
* is not pending in either the cpu irr regs or in the soft irr regs,
|
|
* and the interrupt is not in service, then the interrupt may have
|
|
* been lost. Force an interrupt on that pin. It is possible that
|
|
* the interrupt is in flight, so we may generate a spurious interrupt,
|
|
* but we should never miss a real lost interrupt.
|
|
*/
|
|
static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
|
|
{
|
|
u64 regval;
|
|
struct pcidev_info *pcidev_info;
|
|
struct pcibus_info *pcibus_info;
|
|
|
|
/*
|
|
* Bridge types attached to TIO (anything but PIC) do not need this WAR
|
|
* since they do not target Shub II interrupt registers. If that
|
|
* ever changes, this check needs to accomodate.
|
|
*/
|
|
if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
|
|
return;
|
|
|
|
pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
|
|
if (!pcidev_info)
|
|
return;
|
|
|
|
pcibus_info =
|
|
(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
|
|
pdi_pcibus_info;
|
|
regval = pcireg_intr_status_get(pcibus_info);
|
|
|
|
if (!ia64_get_irr(irq_to_vector(irq))) {
|
|
if (!test_bit(irq, pda->sn_in_service_ivecs)) {
|
|
regval &= 0xff;
|
|
if (sn_irq_info->irq_int_bit & regval &
|
|
sn_irq_info->irq_last_intr) {
|
|
regval &= ~(sn_irq_info->irq_int_bit & regval);
|
|
sn_call_force_intr_provider(sn_irq_info);
|
|
}
|
|
}
|
|
}
|
|
sn_irq_info->irq_last_intr = regval;
|
|
}
|
|
|
|
void sn_lb_int_war_check(void)
|
|
{
|
|
struct sn_irq_info *sn_irq_info;
|
|
int i;
|
|
|
|
if (!sn_ioif_inited || pda->sn_first_irq == 0)
|
|
return;
|
|
|
|
rcu_read_lock();
|
|
for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
|
|
list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
|
|
sn_check_intr(i, sn_irq_info);
|
|
}
|
|
}
|
|
rcu_read_unlock();
|
|
}
|
|
|
|
void __init sn_irq_lh_init(void)
|
|
{
|
|
int i;
|
|
|
|
sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
|
|
if (!sn_irq_lh)
|
|
panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
|
|
|
|
for (i = 0; i < NR_IRQS; i++) {
|
|
sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
|
|
if (!sn_irq_lh[i])
|
|
panic("SN PCI INIT: Failed IRQ memory allocation\n");
|
|
|
|
INIT_LIST_HEAD(sn_irq_lh[i]);
|
|
}
|
|
}
|