940f6b48a1
In particular as-is it's not suited for multicore and mutiprocessors systems where there is on guarantee that the counter are synchronized or running from the same clock at all. This broke Sibyte and probably others since the "[MIPS] Handle R4000/R4400 mfc0 from count register." commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
29 lines
721 B
C
29 lines
721 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 by Ralf Baechle
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*/
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static cycle_t c0_hpt_read(void)
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{
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return read_c0_count();
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}
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static struct clocksource clocksource_mips = {
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.name = "MIPS",
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.read = c0_hpt_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init init_mips_clocksource(void)
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{
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/* Calclate a somewhat reasonable rating value */
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clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
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clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
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clocksource_register(&clocksource_mips);
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}
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