93e1b7d42e
I recently found that not all BIOS manufacturers are using the specified generic PNP id in their TPM ACPI table entry. I have added the vendor specific IDs that I know about and added a module parameter that a user can specify another HID to the probe list if their device isn't being found by the default list. Signed-off-by: Kylene Hall <kjhall@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
669 lines
17 KiB
C
669 lines
17 KiB
C
/*
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* Copyright (C) 2005, 2006 IBM Corporation
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*
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* Authors:
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* Leendert van Doorn <leendert@watson.ibm.com>
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* Kylene Hall <kjhall@us.ibm.com>
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*
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* Device driver for TCG/TCPA TPM (trusted platform module).
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* Specifications at www.trustedcomputinggroup.org
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*
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* This device driver implements the TPM interface as defined in
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* the TCG TPM Interface Spec version 1.2, revision 1.0.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, version 2 of the
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* License.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pnp.h>
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#include <linux/interrupt.h>
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#include <linux/wait.h>
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#include "tpm.h"
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#define TPM_HEADER_SIZE 10
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enum tis_access {
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TPM_ACCESS_VALID = 0x80,
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TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
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TPM_ACCESS_REQUEST_PENDING = 0x04,
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TPM_ACCESS_REQUEST_USE = 0x02,
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};
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enum tis_status {
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TPM_STS_VALID = 0x80,
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TPM_STS_COMMAND_READY = 0x40,
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TPM_STS_GO = 0x20,
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TPM_STS_DATA_AVAIL = 0x10,
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TPM_STS_DATA_EXPECT = 0x08,
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};
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enum tis_int_flags {
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TPM_GLOBAL_INT_ENABLE = 0x80000000,
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TPM_INTF_BURST_COUNT_STATIC = 0x100,
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TPM_INTF_CMD_READY_INT = 0x080,
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TPM_INTF_INT_EDGE_FALLING = 0x040,
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TPM_INTF_INT_EDGE_RISING = 0x020,
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TPM_INTF_INT_LEVEL_LOW = 0x010,
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TPM_INTF_INT_LEVEL_HIGH = 0x008,
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TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
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TPM_INTF_STS_VALID_INT = 0x002,
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TPM_INTF_DATA_AVAIL_INT = 0x001,
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};
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enum tis_defaults {
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TIS_MEM_BASE = 0xFED4000,
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TIS_MEM_LEN = 0x5000,
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TIS_SHORT_TIMEOUT = 750, /* ms */
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TIS_LONG_TIMEOUT = 2000, /* 2 sec */
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};
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#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
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#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
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#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
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#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
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#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
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#define TPM_STS(l) (0x0018 | ((l) << 12))
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#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
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#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
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#define TPM_RID(l) (0x0F04 | ((l) << 12))
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static LIST_HEAD(tis_chips);
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static DEFINE_SPINLOCK(tis_lock);
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static int check_locality(struct tpm_chip *chip, int l)
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{
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if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
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(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
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(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
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return chip->vendor.locality = l;
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return -1;
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}
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static void release_locality(struct tpm_chip *chip, int l, int force)
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{
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if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
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(TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
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(TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
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iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
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chip->vendor.iobase + TPM_ACCESS(l));
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}
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static int request_locality(struct tpm_chip *chip, int l)
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{
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unsigned long stop;
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long rc;
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if (check_locality(chip, l) >= 0)
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return l;
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iowrite8(TPM_ACCESS_REQUEST_USE,
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chip->vendor.iobase + TPM_ACCESS(l));
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if (chip->vendor.irq) {
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rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
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(check_locality
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(chip, l) >= 0),
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chip->vendor.timeout_a);
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if (rc > 0)
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return l;
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} else {
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/* wait for burstcount */
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stop = jiffies + chip->vendor.timeout_a;
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do {
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if (check_locality(chip, l) >= 0)
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return l;
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msleep(TPM_TIMEOUT);
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}
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while (time_before(jiffies, stop));
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}
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return -1;
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}
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static u8 tpm_tis_status(struct tpm_chip *chip)
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{
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return ioread8(chip->vendor.iobase +
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TPM_STS(chip->vendor.locality));
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}
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static void tpm_tis_ready(struct tpm_chip *chip)
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{
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/* this causes the current command to be aborted */
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iowrite8(TPM_STS_COMMAND_READY,
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chip->vendor.iobase + TPM_STS(chip->vendor.locality));
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}
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static int get_burstcount(struct tpm_chip *chip)
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{
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unsigned long stop;
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int burstcnt;
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/* wait for burstcount */
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/* which timeout value, spec has 2 answers (c & d) */
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stop = jiffies + chip->vendor.timeout_d;
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do {
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burstcnt = ioread8(chip->vendor.iobase +
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TPM_STS(chip->vendor.locality) + 1);
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burstcnt += ioread8(chip->vendor.iobase +
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TPM_STS(chip->vendor.locality) +
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2) << 8;
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if (burstcnt)
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return burstcnt;
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msleep(TPM_TIMEOUT);
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} while (time_before(jiffies, stop));
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return -EBUSY;
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}
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static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
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wait_queue_head_t *queue)
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{
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unsigned long stop;
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long rc;
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u8 status;
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/* check current status */
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status = tpm_tis_status(chip);
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if ((status & mask) == mask)
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return 0;
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if (chip->vendor.irq) {
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rc = wait_event_interruptible_timeout(*queue,
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((tpm_tis_status
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(chip) & mask) ==
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mask), timeout);
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if (rc > 0)
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return 0;
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} else {
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stop = jiffies + timeout;
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do {
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msleep(TPM_TIMEOUT);
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status = tpm_tis_status(chip);
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if ((status & mask) == mask)
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return 0;
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} while (time_before(jiffies, stop));
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}
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return -ETIME;
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}
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static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
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{
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int size = 0, burstcnt;
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while (size < count &&
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wait_for_stat(chip,
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TPM_STS_DATA_AVAIL | TPM_STS_VALID,
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chip->vendor.timeout_c,
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&chip->vendor.read_queue)
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== 0) {
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burstcnt = get_burstcount(chip);
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for (; burstcnt > 0 && size < count; burstcnt--)
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buf[size++] = ioread8(chip->vendor.iobase +
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TPM_DATA_FIFO(chip->vendor.
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locality));
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}
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return size;
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}
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static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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{
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int size = 0;
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int expected, status;
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if (count < TPM_HEADER_SIZE) {
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size = -EIO;
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goto out;
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}
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/* read first 10 bytes, including tag, paramsize, and result */
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if ((size =
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recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
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dev_err(chip->dev, "Unable to read header\n");
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goto out;
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}
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expected = be32_to_cpu(*(__be32 *) (buf + 2));
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if (expected > count) {
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size = -EIO;
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goto out;
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}
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if ((size +=
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recv_data(chip, &buf[TPM_HEADER_SIZE],
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expected - TPM_HEADER_SIZE)) < expected) {
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dev_err(chip->dev, "Unable to read remainder of result\n");
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size = -ETIME;
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goto out;
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}
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wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
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&chip->vendor.int_queue);
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status = tpm_tis_status(chip);
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if (status & TPM_STS_DATA_AVAIL) { /* retry? */
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dev_err(chip->dev, "Error left over data\n");
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size = -EIO;
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goto out;
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}
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out:
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tpm_tis_ready(chip);
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release_locality(chip, chip->vendor.locality, 0);
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return size;
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}
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/*
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* If interrupts are used (signaled by an irq set in the vendor structure)
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* tpm.c can skip polling for the data to be available as the interrupt is
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* waited for here
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*/
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static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
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{
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int rc, status, burstcnt;
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size_t count = 0;
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u32 ordinal;
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if (request_locality(chip, 0) < 0)
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return -EBUSY;
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status = tpm_tis_status(chip);
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if ((status & TPM_STS_COMMAND_READY) == 0) {
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tpm_tis_ready(chip);
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if (wait_for_stat
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(chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
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&chip->vendor.int_queue) < 0) {
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rc = -ETIME;
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goto out_err;
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}
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}
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while (count < len - 1) {
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burstcnt = get_burstcount(chip);
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for (; burstcnt > 0 && count < len - 1; burstcnt--) {
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iowrite8(buf[count], chip->vendor.iobase +
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TPM_DATA_FIFO(chip->vendor.locality));
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count++;
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}
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wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
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&chip->vendor.int_queue);
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status = tpm_tis_status(chip);
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if ((status & TPM_STS_DATA_EXPECT) == 0) {
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rc = -EIO;
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goto out_err;
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}
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}
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/* write last byte */
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iowrite8(buf[count],
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chip->vendor.iobase +
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TPM_DATA_FIFO(chip->vendor.locality));
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wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
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&chip->vendor.int_queue);
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status = tpm_tis_status(chip);
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if ((status & TPM_STS_DATA_EXPECT) != 0) {
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rc = -EIO;
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goto out_err;
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}
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/* go and do it */
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iowrite8(TPM_STS_GO,
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chip->vendor.iobase + TPM_STS(chip->vendor.locality));
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if (chip->vendor.irq) {
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ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
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if (wait_for_stat
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(chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID,
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tpm_calc_ordinal_duration(chip, ordinal),
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&chip->vendor.read_queue) < 0) {
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rc = -ETIME;
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goto out_err;
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}
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}
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return len;
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out_err:
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tpm_tis_ready(chip);
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release_locality(chip, chip->vendor.locality, 0);
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return rc;
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}
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static struct file_operations tis_ops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.open = tpm_open,
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.read = tpm_read,
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.write = tpm_write,
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.release = tpm_release,
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};
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static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
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static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
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static DEVICE_ATTR(enabled, S_IRUGO, tpm_show_enabled, NULL);
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static DEVICE_ATTR(active, S_IRUGO, tpm_show_active, NULL);
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static DEVICE_ATTR(owned, S_IRUGO, tpm_show_owned, NULL);
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static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated,
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NULL);
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static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL);
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static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel);
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static struct attribute *tis_attrs[] = {
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&dev_attr_pubek.attr,
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&dev_attr_pcrs.attr,
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&dev_attr_enabled.attr,
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&dev_attr_active.attr,
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&dev_attr_owned.attr,
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&dev_attr_temp_deactivated.attr,
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&dev_attr_caps.attr,
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&dev_attr_cancel.attr, NULL,
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};
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static struct attribute_group tis_attr_grp = {
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.attrs = tis_attrs
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};
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static struct tpm_vendor_specific tpm_tis = {
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.status = tpm_tis_status,
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.recv = tpm_tis_recv,
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.send = tpm_tis_send,
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.cancel = tpm_tis_ready,
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.req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
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.req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
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.req_canceled = TPM_STS_COMMAND_READY,
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.attr_group = &tis_attr_grp,
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.miscdev = {
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.fops = &tis_ops,},
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};
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static irqreturn_t tis_int_probe(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct tpm_chip *chip = (struct tpm_chip *) dev_id;
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u32 interrupt;
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interrupt = ioread32(chip->vendor.iobase +
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TPM_INT_STATUS(chip->vendor.locality));
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if (interrupt == 0)
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return IRQ_NONE;
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chip->vendor.irq = irq;
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/* Clear interrupts handled with TPM_EOI */
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iowrite32(interrupt,
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chip->vendor.iobase +
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TPM_INT_STATUS(chip->vendor.locality));
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return IRQ_HANDLED;
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}
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static irqreturn_t tis_int_handler(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct tpm_chip *chip = (struct tpm_chip *) dev_id;
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u32 interrupt;
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int i;
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interrupt = ioread32(chip->vendor.iobase +
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TPM_INT_STATUS(chip->vendor.locality));
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if (interrupt == 0)
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return IRQ_NONE;
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|
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if (interrupt & TPM_INTF_DATA_AVAIL_INT)
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wake_up_interruptible(&chip->vendor.read_queue);
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if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
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for (i = 0; i < 5; i++)
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if (check_locality(chip, i) >= 0)
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break;
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if (interrupt &
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(TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
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TPM_INTF_CMD_READY_INT))
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wake_up_interruptible(&chip->vendor.int_queue);
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|
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/* Clear interrupts handled with TPM_EOI */
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iowrite32(interrupt,
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chip->vendor.iobase +
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TPM_INT_STATUS(chip->vendor.locality));
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return IRQ_HANDLED;
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}
|
|
|
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static int interrupts = 1;
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module_param(interrupts, bool, 0444);
|
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MODULE_PARM_DESC(interrupts, "Enable interrupts");
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|
|
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static int __devinit tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
|
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const struct pnp_device_id *pnp_id)
|
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{
|
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u32 vendor, intfcaps, intmask;
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int rc, i;
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unsigned long start, len;
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struct tpm_chip *chip;
|
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start = pnp_mem_start(pnp_dev, 0);
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len = pnp_mem_len(pnp_dev, 0);
|
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|
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if (!start)
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start = TIS_MEM_BASE;
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if (!len)
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len = TIS_MEM_LEN;
|
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|
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if (!(chip = tpm_register_hardware(&pnp_dev->dev, &tpm_tis)))
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return -ENODEV;
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|
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chip->vendor.iobase = ioremap(start, len);
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if (!chip->vendor.iobase) {
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rc = -EIO;
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goto out_err;
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}
|
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vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
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if ((vendor & 0xFFFF) == 0xFFFF) {
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rc = -ENODEV;
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goto out_err;
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}
|
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|
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/* Default timeouts */
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chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
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chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
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chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
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chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
|
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|
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dev_info(&pnp_dev->dev,
|
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"1.2 TPM (device-id 0x%X, rev-id %d)\n",
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vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
|
|
|
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/* Figure out the capabilities */
|
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intfcaps =
|
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ioread32(chip->vendor.iobase +
|
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TPM_INTF_CAPS(chip->vendor.locality));
|
|
dev_dbg(&pnp_dev->dev, "TPM interface capabilities (0x%x):\n",
|
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intfcaps);
|
|
if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
|
|
dev_dbg(&pnp_dev->dev, "\tBurst Count Static\n");
|
|
if (intfcaps & TPM_INTF_CMD_READY_INT)
|
|
dev_dbg(&pnp_dev->dev, "\tCommand Ready Int Support\n");
|
|
if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
|
|
dev_dbg(&pnp_dev->dev, "\tInterrupt Edge Falling\n");
|
|
if (intfcaps & TPM_INTF_INT_EDGE_RISING)
|
|
dev_dbg(&pnp_dev->dev, "\tInterrupt Edge Rising\n");
|
|
if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
|
|
dev_dbg(&pnp_dev->dev, "\tInterrupt Level Low\n");
|
|
if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
|
|
dev_dbg(&pnp_dev->dev, "\tInterrupt Level High\n");
|
|
if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
|
|
dev_dbg(&pnp_dev->dev, "\tLocality Change Int Support\n");
|
|
if (intfcaps & TPM_INTF_STS_VALID_INT)
|
|
dev_dbg(&pnp_dev->dev, "\tSts Valid Int Support\n");
|
|
if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
|
|
dev_dbg(&pnp_dev->dev, "\tData Avail Int Support\n");
|
|
|
|
if (request_locality(chip, 0) != 0) {
|
|
rc = -ENODEV;
|
|
goto out_err;
|
|
}
|
|
|
|
/* INTERRUPT Setup */
|
|
init_waitqueue_head(&chip->vendor.read_queue);
|
|
init_waitqueue_head(&chip->vendor.int_queue);
|
|
|
|
intmask =
|
|
ioread32(chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
|
|
intmask |= TPM_INTF_CMD_READY_INT
|
|
| TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
|
|
| TPM_INTF_STS_VALID_INT;
|
|
|
|
iowrite32(intmask,
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
if (interrupts) {
|
|
chip->vendor.irq =
|
|
ioread8(chip->vendor.iobase +
|
|
TPM_INT_VECTOR(chip->vendor.locality));
|
|
|
|
for (i = 3; i < 16 && chip->vendor.irq == 0; i++) {
|
|
iowrite8(i, chip->vendor.iobase +
|
|
TPM_INT_VECTOR(chip->vendor.locality));
|
|
if (request_irq
|
|
(i, tis_int_probe, SA_SHIRQ,
|
|
chip->vendor.miscdev.name, chip) != 0) {
|
|
dev_info(chip->dev,
|
|
"Unable to request irq: %d for probe\n",
|
|
i);
|
|
continue;
|
|
}
|
|
|
|
/* Clear all existing */
|
|
iowrite32(ioread32
|
|
(chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality)),
|
|
chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
|
|
/* Turn on */
|
|
iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
|
|
/* Generate Interrupts */
|
|
tpm_gen_interrupt(chip);
|
|
|
|
/* Turn off */
|
|
iowrite32(intmask,
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
free_irq(i, chip);
|
|
}
|
|
}
|
|
if (chip->vendor.irq) {
|
|
iowrite8(chip->vendor.irq,
|
|
chip->vendor.iobase +
|
|
TPM_INT_VECTOR(chip->vendor.locality));
|
|
if (request_irq
|
|
(chip->vendor.irq, tis_int_handler, SA_SHIRQ,
|
|
chip->vendor.miscdev.name, chip) != 0) {
|
|
dev_info(chip->dev,
|
|
"Unable to request irq: %d for use\n",
|
|
chip->vendor.irq);
|
|
chip->vendor.irq = 0;
|
|
} else {
|
|
/* Clear all existing */
|
|
iowrite32(ioread32
|
|
(chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality)),
|
|
chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
|
|
/* Turn on */
|
|
iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
}
|
|
}
|
|
|
|
INIT_LIST_HEAD(&chip->vendor.list);
|
|
spin_lock(&tis_lock);
|
|
list_add(&chip->vendor.list, &tis_chips);
|
|
spin_unlock(&tis_lock);
|
|
|
|
tpm_get_timeouts(chip);
|
|
tpm_continue_selftest(chip);
|
|
|
|
return 0;
|
|
out_err:
|
|
if (chip->vendor.iobase)
|
|
iounmap(chip->vendor.iobase);
|
|
tpm_remove_hardware(chip->dev);
|
|
return rc;
|
|
}
|
|
|
|
static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
|
|
{
|
|
return tpm_pm_suspend(&dev->dev, msg);
|
|
}
|
|
|
|
static int tpm_tis_pnp_resume(struct pnp_dev *dev)
|
|
{
|
|
return tpm_pm_resume(&dev->dev);
|
|
}
|
|
|
|
static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {
|
|
{"PNP0C31", 0}, /* TPM */
|
|
{"ATM1200", 0}, /* Atmel */
|
|
{"IFX0102", 0}, /* Infineon */
|
|
{"BCM0101", 0}, /* Broadcom */
|
|
{"NSC1200", 0}, /* National */
|
|
/* Add new here */
|
|
{"", 0}, /* User Specified */
|
|
{"", 0} /* Terminator */
|
|
};
|
|
|
|
static struct pnp_driver tis_pnp_driver = {
|
|
.name = "tpm_tis",
|
|
.id_table = tpm_pnp_tbl,
|
|
.probe = tpm_tis_pnp_init,
|
|
.suspend = tpm_tis_pnp_suspend,
|
|
.resume = tpm_tis_pnp_resume,
|
|
};
|
|
|
|
#define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2
|
|
module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id,
|
|
sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444);
|
|
MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe");
|
|
|
|
static int __init init_tis(void)
|
|
{
|
|
return pnp_register_driver(&tis_pnp_driver);
|
|
}
|
|
|
|
static void __exit cleanup_tis(void)
|
|
{
|
|
struct tpm_vendor_specific *i, *j;
|
|
struct tpm_chip *chip;
|
|
spin_lock(&tis_lock);
|
|
list_for_each_entry_safe(i, j, &tis_chips, list) {
|
|
chip = to_tpm_chip(i);
|
|
iowrite32(~TPM_GLOBAL_INT_ENABLE &
|
|
ioread32(chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.
|
|
locality)),
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
release_locality(chip, chip->vendor.locality, 1);
|
|
if (chip->vendor.irq)
|
|
free_irq(chip->vendor.irq, chip);
|
|
iounmap(i->iobase);
|
|
list_del(&i->list);
|
|
tpm_remove_hardware(chip->dev);
|
|
}
|
|
spin_unlock(&tis_lock);
|
|
pnp_unregister_driver(&tis_pnp_driver);
|
|
}
|
|
|
|
module_init(init_tis);
|
|
module_exit(cleanup_tis);
|
|
MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
|
|
MODULE_DESCRIPTION("TPM Driver");
|
|
MODULE_VERSION("2.0");
|
|
MODULE_LICENSE("GPL");
|