5f79c651e8
The Armada XP GPIO controller has two ways of notifying interrupts: using global interrupts or using per-CPU interrupts. In an attempt to use the best available features, the 'marvell,armadaxp-gpio' compatible string selects a variant of the gpio-mvebu driver that makes use of the per-CPU interrupts. Unfortunately, this doesn't work properly in a SMP context, because we fall into cases where the GPIO interrupt is enabled on CPU X at the GPIO controller level, but on CPU Y at the interrupt controller level. It is not yet clear how to fix that easily. So for 3.8, our approach is to switch to global interrupts for GPIOs, so that we do not fall into this per-CPU interrupts problem. This patch therefore fixes GPIO interrupts on Armada XP platforms. Without this patch, GPIO interrupts simply do not work reliably, because their proper operation depends on which CPU the code requesting the interrupt is running. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
109 lines
2.2 KiB
Text
109 lines
2.2 KiB
Text
/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada XP MV78460 SoC that are not
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* common to all Armada XP SoCs.
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*/
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/include/ "armada-xp.dtsi"
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/ {
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model = "Marvell Armada XP MV78460 SoC";
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compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <1>;
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clocks = <&cpuclk 1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <2>;
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clocks = <&cpuclk 2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <3>;
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clocks = <&cpuclk 3>;
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};
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};
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soc {
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pinctrl {
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compatible = "marvell,mv78460-pinctrl";
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reg = <0xd0018000 0x38>;
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};
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gpio0: gpio@d0018100 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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gpio1: gpio@d0018140 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018140 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <87>, <88>, <89>, <90>;
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};
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gpio2: gpio@d0018180 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018180 0x40>;
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ngpios = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <91>;
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};
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ethernet@d0034000 {
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compatible = "marvell,armada-370-neta";
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reg = <0xd0034000 0x2500>;
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interrupts = <14>;
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clocks = <&gateclk 1>;
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status = "disabled";
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};
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};
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};
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