kernel-fxtec-pro1x/arch/m32r/mm/cache.c
Hirokazu Takata 9287d95ea1 [PATCH] m32r: Support M32104UT target platform
This patch is for supporting a new target platform, Renesas M32104UT
evaluation board.

The M32104UT is an eval board based on an uT-Engine specification.  This board
has an MMU-less M32R family processor, M32104.
http://www-wa0.personal-media.co.jp/pmc/archive/te/te_m32104_e.pdf

This board is one of the most popular M32R platform, so we have ported
Linux/M32R to it.

Signed-off-by: Naoto Sugai <Sugai.Naoto@ak.MitsubishiElectric.co.jp>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-06 08:33:43 -08:00

75 lines
2.3 KiB
C

/*
* linux/arch/m32r/mm/cache.c
*
* Copyright (C) 2002 Hirokazu Takata
*/
#include <linux/config.h>
#include <asm/pgtable.h>
#undef MCCR
#if defined(CONFIG_CHIP_XNUX2) || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_OPSP)
/* Cache Control Register */
#define MCCR ((volatile unsigned long*)0xfffffffc)
#define MCCR_CC (1UL << 7) /* Cache mode modify bit */
#define MCCR_IIV (1UL << 6) /* I-cache invalidate */
#define MCCR_DIV (1UL << 5) /* D-cache invalidate */
#define MCCR_DCB (1UL << 4) /* D-cache copy back */
#define MCCR_ICM (1UL << 1) /* I-cache mode [0:off,1:on] */
#define MCCR_DCM (1UL << 0) /* D-cache mode [0:off,1:on] */
#define MCCR_ICACHE_INV (MCCR_CC|MCCR_IIV)
#define MCCR_DCACHE_CB (MCCR_CC|MCCR_DCB)
#define MCCR_DCACHE_CBINV (MCCR_CC|MCCR_DIV|MCCR_DCB)
#define CHECK_MCCR(mccr) (mccr = *MCCR)
#elif defined(CONFIG_CHIP_M32102)
#define MCCR ((volatile unsigned char*)0xfffffffe)
#define MCCR_IIV (1UL << 0) /* I-cache invalidate */
#define MCCR_ICACHE_INV MCCR_IIV
#elif defined(CONFIG_CHIP_M32104)
#define MCCR ((volatile unsigned long*)0xfffffffc)
#define MCCR_IIV (1UL << 8) /* I-cache invalidate */
#define MCCR_DIV (1UL << 9) /* D-cache invalidate */
#define MCCR_DCB (1UL << 10) /* D-cache copy back */
#define MCCR_ICM (1UL << 0) /* I-cache mode [0:off,1:on] */
#define MCCR_DCM (1UL << 1) /* D-cache mode [0:off,1:on] */
#define MCCR_ICACHE_INV MCCR_IIV
#define MCCR_DCACHE_CB MCCR_DCB
#define MCCR_DCACHE_CBINV (MCCR_DIV|MCCR_DCB)
#endif /* CONFIG_CHIP_XNUX2 || CONFIG_CHIP_M32700 */
#ifndef MCCR
#error Unknown cache type.
#endif
/* Copy back and invalidate D-cache and invalidate I-cache all */
void _flush_cache_all(void)
{
#if defined(CONFIG_CHIP_M32102)
*MCCR = MCCR_ICACHE_INV;
#else
unsigned long mccr;
/* Copyback and invalidate D-cache */
/* Invalidate I-cache */
*MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CBINV;
while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
#endif
}
/* Copy back D-cache and invalidate I-cache all */
void _flush_cache_copyback_all(void)
{
#if defined(CONFIG_CHIP_M32102)
*MCCR = MCCR_ICACHE_INV;
#else
unsigned long mccr;
/* Copyback D-cache */
/* Invalidate I-cache */
*MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CB;
while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
#endif
}