6b4cd27550
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/*
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* Copyright 2001, 2002, 2003 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Common time service routines for MIPS machines. See
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* Documents/MIPS/README.txt.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/param.h>
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#include <linux/time.h>
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#include <linux/timer.h>
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#include <linux/smp.h>
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#include <linux/kernel_stat.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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#include <asm/time.h>
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#include <asm/hardirq.h>
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#include <asm/div64.h>
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#include <asm/debug.h>
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#include <int.h>
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#include <cm.h>
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static unsigned long cpj;
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static cycle_t hpt_read(void)
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{
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return read_c0_count2();
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}
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static void timer_ack(void)
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{
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write_c0_compare(cpj);
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}
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/*
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* pnx8550_time_init() - it does the following things:
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*
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* 1) board_time_init() -
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* a) (optional) set up RTC routines,
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* b) (optional) calibrate and set the mips_hpt_frequency
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* (only needed if you intended to use cpu counter as timer interrupt
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* source)
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*/
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void pnx8550_time_init(void)
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{
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unsigned int n;
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unsigned int m;
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unsigned int p;
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unsigned int pow2p;
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/* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
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/* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */
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n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
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m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
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p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
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pow2p = (1 << p);
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db_assert(m != 0 && pow2p != 0);
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/*
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* Compute the frequency as in the PNX8550 User Manual 1.0, p.186
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* (a.k.a. 8-10). Divide by HZ for a timer offset that results in
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* HZ timer interrupts per second.
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*/
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mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
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cpj = (mips_hpt_frequency + HZ / 2) / HZ;
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write_c0_count(0);
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timer_ack();
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/* Setup Timer 2 */
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write_c0_count2(0);
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write_c0_compare2(0xffffffff);
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clocksource_mips.read = hpt_read;
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mips_timer_ack = timer_ack;
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}
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static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
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{
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/* Timer 2 clear interrupt */
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write_c0_compare2(-1);
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return IRQ_HANDLED;
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}
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static struct irqaction monotonic_irqaction = {
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.handler = monotonic_interrupt,
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.flags = IRQF_DISABLED,
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.name = "Monotonic timer",
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};
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void __init plat_timer_setup(struct irqaction *irq)
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{
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int configPR;
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setup_irq(PNX8550_INT_TIMER1, irq);
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setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
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/* Timer 1 start */
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configPR = read_c0_config7();
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configPR &= ~0x00000008;
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write_c0_config7(configPR);
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/* Timer 2 start */
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configPR = read_c0_config7();
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configPR &= ~0x00000010;
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write_c0_config7(configPR);
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/* Timer 3 stop */
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configPR = read_c0_config7();
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configPR |= 0x00000020;
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write_c0_config7(configPR);
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}
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