714d8e7e27
The main change here is a significant head.S rework that allows us to boot on machines with physical memory at a really high address without having to increase our mapped VA range. Other changes include: - AES performance boost for Cortex-A57 - AArch32 (compat) userspace with 64k pages - Cortex-A53 erratum workaround for #845719 - defconfig updates (new platforms, PCI, ...) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJVLnQpAAoJELescNyEwWM03RIH/iwcDc0MBZgkwfD5cnY+29p4 m89lMDo3SyGQT4NynHSw7P3R7c3zULmI+9hmJMw/yfjjjL6m7X+vVAF3xj1Am4Al OzCqYLHyFnlRktzJ6dWeF1Ese7tWqPpxn+OCXgYNpz/r5MfF/HhlyX/qNzAQPKrw ZpDvnt44DgUfweqjTbwQUg2wkyCRjmz57MQYxDcmJStdpHIu24jWOvDIo3OJGjyS L49I9DU6DGUhkISZmmBE0T7vmKMD1BcgI7OIzX2WIqn521QT+GSLMhRxaHmK1s1V A8gaMTwpo0xFhTAt7sbw/5+2663WmfRdZI+FtduvORsoxX6KdDn7DH1NQixIm8s= =+F0I -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Will Deacon: "Here are the core arm64 updates for 4.1. Highlights include a significant rework to head.S (allowing us to boot on machines with physical memory at a really high address), an AES performance boost on Cortex-A57 and the ability to run a 32-bit userspace with 64k pages (although this requires said userspace to be built with a recent binutils). The head.S rework spilt over into KVM, so there are some changes under arch/arm/ which have been acked by Marc Zyngier (KVM co-maintainer). In particular, the linker script changes caused us some issues in -next, so there are a few merge commits where we had to apply fixes on top of a stable branch. Other changes include: - AES performance boost for Cortex-A57 - AArch32 (compat) userspace with 64k pages - Cortex-A53 erratum workaround for #845719 - defconfig updates (new platforms, PCI, ...)" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (39 commits) arm64: fix midr range for Cortex-A57 erratum 832075 arm64: errata: add workaround for cortex-a53 erratum #845719 arm64: Use bool function return values of true/false not 1/0 arm64: defconfig: updates for 4.1 arm64: Extract feature parsing code from cpu_errata.c arm64: alternative: Allow immediate branch as alternative instruction arm64: insn: Add aarch64_insn_decode_immediate ARM: kvm: round HYP section to page size instead of log2 upper bound ARM: kvm: assert on HYP section boundaries not actual code size arm64: head.S: ensure idmap_t0sz is visible arm64: pmu: add support for interrupt-affinity property dt: pmu: extend ARM PMU binding to allow for explicit interrupt affinity arm64: head.S: ensure visibility of page tables arm64: KVM: use ID map with increased VA range if required arm64: mm: increase VA range of identity map ARM: kvm: implement replacement for ld's LOG2CEIL() arm64: proc: remove unused cpu_get_pgd macro arm64: enforce x1|x2|x3 == 0 upon kernel entry as per boot protocol arm64: remove __calc_phys_offset arm64: merge __enable_mmu and __turn_mmu_on ...
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/*
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* Based on arch/arm/include/asm/page.h
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*
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* Copyright (C) 1995-2003 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PAGE_H
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#define __ASM_PAGE_H
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/* PAGE_SHIFT determines the page size */
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#ifdef CONFIG_ARM64_64K_PAGES
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#define PAGE_SHIFT 16
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#else
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#define PAGE_SHIFT 12
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#endif
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#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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/*
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* The idmap and swapper page tables need some space reserved in the kernel
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* image. Both require pgd, pud (4 levels only) and pmd tables to (section)
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* map the kernel. With the 64K page configuration, swapper and idmap need to
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* map to pte level. The swapper also maps the FDT (see __create_page_tables
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* for more information). Note that the number of ID map translation levels
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* could be increased on the fly if system RAM is out of reach for the default
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* VA range, so 3 pages are reserved in all cases.
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*/
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#ifdef CONFIG_ARM64_64K_PAGES
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#define SWAPPER_PGTABLE_LEVELS (CONFIG_PGTABLE_LEVELS)
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#else
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#define SWAPPER_PGTABLE_LEVELS (CONFIG_PGTABLE_LEVELS - 1)
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#endif
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#define SWAPPER_DIR_SIZE (SWAPPER_PGTABLE_LEVELS * PAGE_SIZE)
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#define IDMAP_DIR_SIZE (3 * PAGE_SIZE)
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#ifndef __ASSEMBLY__
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#include <asm/pgtable-types.h>
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extern void __cpu_clear_user_page(void *p, unsigned long user);
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extern void __cpu_copy_user_page(void *to, const void *from,
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unsigned long user);
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extern void copy_page(void *to, const void *from);
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extern void clear_page(void *to);
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#define clear_user_page(addr,vaddr,pg) __cpu_clear_user_page(addr, vaddr)
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#define copy_user_page(to,from,vaddr,pg) __cpu_copy_user_page(to, from, vaddr)
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typedef struct page *pgtable_t;
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#ifdef CONFIG_HAVE_ARCH_PFN_VALID
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extern int pfn_valid(unsigned long);
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#endif
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#include <asm/memory.h>
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#endif /* !__ASSEMBLY__ */
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#define VM_DATA_DEFAULT_FLAGS \
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(((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
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VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#include <asm-generic/getorder.h>
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#endif
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