f45913fde0
We have a handy macro to replace open coded __cpuc_flush_dcache_area(() and outer_clean_range() sequences. Let's use it. No functional change. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
91 lines
2.1 KiB
C
91 lines
2.1 KiB
C
/*
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* linux/arch/arm/plat-versatile/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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sync_cache_w(&pen_release);
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}
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static DEFINE_SPINLOCK(boot_lock);
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void versatile_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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* CPUs in the holding pen until we're ready for them. However,
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* since we haven't sent them a soft interrupt, they shouldn't
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* be there.
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*/
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write_pen_release(cpu_logical_map(cpu));
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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