b8db6b886a
Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as: - no cache id part number available through hardware (need to get it by the DT). - always write through mode available. - two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation). - in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line. Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* AURORA shared L2 cache controller support
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*
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* Copyright (C) 2012 Marvell
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*
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
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#define __ASM_ARM_HARDWARE_AURORA_L2_H
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#define AURORA_SYNC_REG 0x700
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#define AURORA_RANGE_BASE_ADDR_REG 0x720
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#define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
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#define AURORA_INVAL_RANGE_REG 0x774
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#define AURORA_CLEAN_RANGE_REG 0x7b4
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#define AURORA_FLUSH_RANGE_REG 0x7f4
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#define AURORA_ACR_REPLACEMENT_OFFSET 27
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#define AURORA_ACR_REPLACEMENT_MASK \
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(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
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#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR \
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(0 << AURORA_ACR_REPLACEMENT_OFFSET)
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#define AURORA_ACR_REPLACEMENT_TYPE_LFSR \
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(1 << AURORA_ACR_REPLACEMENT_OFFSET)
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#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
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(3 << AURORA_ACR_REPLACEMENT_OFFSET)
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#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
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#define AURORA_ACR_FORCE_WRITE_POLICY_MASK \
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(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
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#define AURORA_ACR_FORCE_WRITE_POLICY_DIS \
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(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
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#define AURORA_ACR_FORCE_WRITE_BACK_POLICY \
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(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
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#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \
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(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
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#define MAX_RANGE_SIZE 1024
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#define AURORA_WAY_SIZE_SHIFT 2
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#define AURORA_CTRL_FW 0x100
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/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
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* the distinction between a number coming from hardware and a number
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* coming from the device tree */
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#define AURORA_CACHE_ID 0x100
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#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
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