d8f6098d5b
make defconfig give the following error on ppc (gcc-4): arch/ppc/syslib/open_pic.c:36: error: static declaration of ‘OpenPIC’ follows non-static declaration arch/ppc/syslib/open_pic_defs.h:175: error: previous declaration of ‘OpenPIC’ was here Signed-Off-By: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
289 lines
7.2 KiB
C
289 lines
7.2 KiB
C
/*
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* arch/ppc/kernel/open_pic_defs.h -- OpenPIC definitions
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*
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* Copyright (C) 1997 Geert Uytterhoeven
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*
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* This file is based on the following documentation:
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*
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* The Open Programmable Interrupt Controller (PIC)
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* Register Interface Specification Revision 1.2
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*
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* Issue Date: October 1995
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*
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* Issued jointly by Advanced Micro Devices and Cyrix Corporation
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*
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* AMD is a registered trademark of Advanced Micro Devices, Inc.
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* Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
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* All Rights Reserved.
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*
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* To receive a copy of this documentation, send an email to openpic@amd.com.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#ifndef _LINUX_OPENPIC_H
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#define _LINUX_OPENPIC_H
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#ifdef __KERNEL__
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/*
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* OpenPIC supports up to 2048 interrupt sources and up to 32 processors
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*/
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#define OPENPIC_MAX_SOURCES 2048
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#define OPENPIC_MAX_PROCESSORS 32
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#define OPENPIC_MAX_ISU 16
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#define OPENPIC_NUM_TIMERS 4
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#define OPENPIC_NUM_IPI 4
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#define OPENPIC_NUM_PRI 16
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#define OPENPIC_NUM_VECTORS 256
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/*
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* OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
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*/
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typedef struct _OpenPIC_Reg {
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u_int Reg; /* Little endian! */
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char Pad[0xc];
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} OpenPIC_Reg;
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/*
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* Per Processor Registers
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*/
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typedef struct _OpenPIC_Processor {
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/*
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* Private Shadow Registers (for SLiC backwards compatibility)
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*/
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u_int IPI0_Dispatch_Shadow; /* Write Only */
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char Pad1[0x4];
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u_int IPI0_Vector_Priority_Shadow; /* Read/Write */
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char Pad2[0x34];
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/*
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* Interprocessor Interrupt Command Ports
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*/
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OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
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/*
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* Current Task Priority Register
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*/
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OpenPIC_Reg _Current_Task_Priority; /* Read/Write */
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char Pad3[0x10];
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/*
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* Interrupt Acknowledge Register
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*/
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OpenPIC_Reg _Interrupt_Acknowledge; /* Read Only */
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/*
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* End of Interrupt (EOI) Register
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*/
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OpenPIC_Reg _EOI; /* Read/Write */
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char Pad5[0xf40];
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} OpenPIC_Processor;
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/*
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* Timer Registers
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*/
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typedef struct _OpenPIC_Timer {
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OpenPIC_Reg _Current_Count; /* Read Only */
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OpenPIC_Reg _Base_Count; /* Read/Write */
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OpenPIC_Reg _Vector_Priority; /* Read/Write */
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OpenPIC_Reg _Destination; /* Read/Write */
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} OpenPIC_Timer;
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/*
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* Global Registers
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*/
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typedef struct _OpenPIC_Global {
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/*
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* Feature Reporting Registers
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*/
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OpenPIC_Reg _Feature_Reporting0; /* Read Only */
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OpenPIC_Reg _Feature_Reporting1; /* Future Expansion */
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/*
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* Global Configuration Registers
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*/
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OpenPIC_Reg _Global_Configuration0; /* Read/Write */
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OpenPIC_Reg _Global_Configuration1; /* Future Expansion */
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/*
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* Vendor Specific Registers
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*/
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OpenPIC_Reg _Vendor_Specific[4];
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/*
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* Vendor Identification Register
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*/
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OpenPIC_Reg _Vendor_Identification; /* Read Only */
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/*
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* Processor Initialization Register
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*/
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OpenPIC_Reg _Processor_Initialization; /* Read/Write */
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/*
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* IPI Vector/Priority Registers
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*/
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OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI]; /* Read/Write */
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/*
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* Spurious Vector Register
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*/
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OpenPIC_Reg _Spurious_Vector; /* Read/Write */
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/*
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* Global Timer Registers
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*/
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OpenPIC_Reg _Timer_Frequency; /* Read/Write */
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OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
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char Pad1[0xee00];
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} OpenPIC_Global;
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/*
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* Interrupt Source Registers
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*/
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typedef struct _OpenPIC_Source {
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OpenPIC_Reg _Vector_Priority; /* Read/Write */
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OpenPIC_Reg _Destination; /* Read/Write */
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} OpenPIC_Source, *OpenPIC_SourcePtr;
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/*
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* OpenPIC Register Map
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*/
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struct OpenPIC {
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char Pad1[0x1000];
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/*
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* Global Registers
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*/
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OpenPIC_Global Global;
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/*
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* Interrupt Source Configuration Registers
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*/
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OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
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/*
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* Per Processor Registers
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*/
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OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
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};
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/*
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* Current Task Priority Register
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*/
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#define OPENPIC_CURRENT_TASK_PRIORITY_MASK 0x0000000f
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/*
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* Who Am I Register
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*/
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#define OPENPIC_WHO_AM_I_ID_MASK 0x0000001f
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/*
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* Feature Reporting Register 0
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*/
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#define OPENPIC_FEATURE_LAST_SOURCE_MASK 0x07ff0000
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#define OPENPIC_FEATURE_LAST_SOURCE_SHIFT 16
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#define OPENPIC_FEATURE_LAST_PROCESSOR_MASK 0x00001f00
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#define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT 8
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#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff
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/*
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* Global Configuration Register 0
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*/
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#define OPENPIC_CONFIG_RESET 0x80000000
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#define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
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#define OPENPIC_CONFIG_BASE_MASK 0x000fffff
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/*
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* Global Configuration Register 1
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* This is the EICR on EPICs.
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*/
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#define OPENPIC_EICR_S_CLK_MASK 0x70000000
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#define OPENPIC_EICR_SIE 0x08000000
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/*
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* Vendor Identification Register
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*/
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#define OPENPIC_VENDOR_ID_STEPPING_MASK 0x00ff0000
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#define OPENPIC_VENDOR_ID_STEPPING_SHIFT 16
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#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
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#define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT 8
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#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
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/*
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* Vector/Priority Registers
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*/
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#define OPENPIC_MASK 0x80000000
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#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */
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#define OPENPIC_PRIORITY_MASK 0x000f0000
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#define OPENPIC_PRIORITY_SHIFT 16
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#define OPENPIC_VECTOR_MASK 0x000000ff
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/*
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* Interrupt Source Registers
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*/
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#define OPENPIC_POLARITY_POSITIVE 0x00800000
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#define OPENPIC_POLARITY_NEGATIVE 0x00000000
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#define OPENPIC_POLARITY_MASK 0x00800000
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#define OPENPIC_SENSE_LEVEL 0x00400000
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#define OPENPIC_SENSE_EDGE 0x00000000
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#define OPENPIC_SENSE_MASK 0x00400000
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/*
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* Timer Registers
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*/
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#define OPENPIC_COUNT_MASK 0x7fffffff
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#define OPENPIC_TIMER_TOGGLE 0x80000000
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#define OPENPIC_TIMER_COUNT_INHIBIT 0x80000000
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/*
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* Aliases to make life simpler
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*/
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/* Per Processor Registers */
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#define IPI_Dispatch(i) _IPI_Dispatch[i].Reg
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#define Current_Task_Priority _Current_Task_Priority.Reg
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#define Interrupt_Acknowledge _Interrupt_Acknowledge.Reg
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#define EOI _EOI.Reg
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/* Global Registers */
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#define Feature_Reporting0 _Feature_Reporting0.Reg
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#define Feature_Reporting1 _Feature_Reporting1.Reg
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#define Global_Configuration0 _Global_Configuration0.Reg
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#define Global_Configuration1 _Global_Configuration1.Reg
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#define Vendor_Specific(i) _Vendor_Specific[i].Reg
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#define Vendor_Identification _Vendor_Identification.Reg
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#define Processor_Initialization _Processor_Initialization.Reg
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#define IPI_Vector_Priority(i) _IPI_Vector_Priority[i].Reg
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#define Spurious_Vector _Spurious_Vector.Reg
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#define Timer_Frequency _Timer_Frequency.Reg
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/* Timer Registers */
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#define Current_Count _Current_Count.Reg
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#define Base_Count _Base_Count.Reg
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#define Vector_Priority _Vector_Priority.Reg
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#define Destination _Destination.Reg
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/* Interrupt Source Registers */
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#define Vector_Priority _Vector_Priority.Reg
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#define Destination _Destination.Reg
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#endif /* __KERNEL__ */
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#endif /* _LINUX_OPENPIC_H */
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