0c3263870f
This includes conversion to new style irq_chip functions, and
correctly enabling/disabling per-CPU interrupts.
The hardware interrupt bit to irq number mapping is now done with a
flexible map, instead of by bit twiddling the irq number.
[ tglx: Adjusted to new irq_cpu_on/offline callbacks and
__irq_set_affinity_lock ]
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
LKML-Reference: <1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
101 lines
2.8 KiB
C
101 lines
2.8 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008 Cavium Networks
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*/
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#ifndef __OCTEON_IRQ_H__
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#define __OCTEON_IRQ_H__
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#define NR_IRQS OCTEON_IRQ_LAST
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#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
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enum octeon_irq {
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/* 1 - 8 represent the 8 MIPS standard interrupt sources */
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OCTEON_IRQ_SW0 = 1,
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OCTEON_IRQ_SW1,
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/* CIU0, CUI2, CIU4 are 3, 4, 5 */
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OCTEON_IRQ_5 = 6,
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OCTEON_IRQ_PERF,
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OCTEON_IRQ_TIMER,
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/* sources in CIU_INTX_EN0 */
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OCTEON_IRQ_WORKQ0,
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OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
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OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
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OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
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OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
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OCTEON_IRQ_MBOX1,
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OCTEON_IRQ_UART0,
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OCTEON_IRQ_UART1,
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OCTEON_IRQ_UART2,
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OCTEON_IRQ_PCI_INT0,
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OCTEON_IRQ_PCI_INT1,
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OCTEON_IRQ_PCI_INT2,
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OCTEON_IRQ_PCI_INT3,
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OCTEON_IRQ_PCI_MSI0,
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OCTEON_IRQ_PCI_MSI1,
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OCTEON_IRQ_PCI_MSI2,
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OCTEON_IRQ_PCI_MSI3,
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OCTEON_IRQ_TWSI,
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OCTEON_IRQ_TWSI2,
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OCTEON_IRQ_RML,
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OCTEON_IRQ_TRACE0,
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OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
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OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
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OCTEON_IRQ_KEY_ZERO,
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OCTEON_IRQ_TIMER0,
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OCTEON_IRQ_TIMER1,
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OCTEON_IRQ_TIMER2,
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OCTEON_IRQ_TIMER3,
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OCTEON_IRQ_USB0,
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OCTEON_IRQ_USB1,
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OCTEON_IRQ_PCM,
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OCTEON_IRQ_MPI,
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OCTEON_IRQ_POWIQ,
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OCTEON_IRQ_IPDPPTHR,
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OCTEON_IRQ_MII0,
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OCTEON_IRQ_MII1,
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OCTEON_IRQ_BOOTDMA,
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OCTEON_IRQ_NAND,
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OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */
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OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */
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OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */
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OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */
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OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */
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OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */
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OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */
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OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */
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OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */
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OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */
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OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */
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OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */
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OCTEON_IRQ_DFA, /* Summary of DFA */
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OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */
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OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */
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OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */
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OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */
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OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5,
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OCTEON_IRQ_PTP,
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OCTEON_IRQ_PEM0,
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OCTEON_IRQ_PEM1,
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OCTEON_IRQ_SRIO0,
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OCTEON_IRQ_SRIO1,
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OCTEON_IRQ_LMC0,
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OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */
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OCTEON_IRQ_RST,
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};
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#ifdef CONFIG_PCI_MSI
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/* 152 - 407 represent the MSI interrupts 0-255 */
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#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1)
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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#else
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1)
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#endif
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#endif
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