881ccccb6b
The ARM arch_{read,write}_trylock implementations include unused
backwards branch labels, since we don't retry the locking operation
if the exclusive store fails.
This patch removes the labels.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
292 lines
6 KiB
C
292 lines
6 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#if __LINUX_ARM_ARCH__ < 6
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#error SMP not supported on pre-ARMv6 CPUs
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#endif
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#include <asm/processor.h>
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/*
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* sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K
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* extensions, so when running on UP, we have to patch these instructions away.
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*/
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#define ALT_SMP(smp, up) \
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"9998: " smp "\n" \
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" .pushsection \".alt.smp.init\", \"a\"\n" \
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" .long 9998b\n" \
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" " up "\n" \
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" .popsection\n"
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#ifdef CONFIG_THUMB2_KERNEL
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#define SEV ALT_SMP("sev.w", "nop.w")
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/*
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* For Thumb-2, special care is needed to ensure that the conditional WFE
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* instruction really does assemble to exactly 4 bytes (as required by
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* the SMP_ON_UP fixup code). By itself "wfene" might cause the
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* assembler to insert a extra (16-bit) IT instruction, depending on the
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* presence or absence of neighbouring conditional instructions.
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*
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* To avoid this unpredictableness, an approprite IT is inserted explicitly:
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* the assembler won't change IT instructions which are explicitly present
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* in the input.
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*/
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#define WFE(cond) ALT_SMP( \
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"it " cond "\n\t" \
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"wfe" cond ".n", \
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\
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"nop.w" \
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)
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#else
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#define SEV ALT_SMP("sev", "nop")
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#define WFE(cond) ALT_SMP("wfe" cond, "nop")
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#endif
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static inline void dsb_sev(void)
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{
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#if __LINUX_ARM_ARCH__ >= 7
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__asm__ __volatile__ (
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"dsb\n"
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SEV
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);
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#else
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__asm__ __volatile__ (
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"mcr p15, 0, %0, c7, c10, 4\n"
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SEV
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: : "r" (0)
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);
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#endif
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}
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/*
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* ARMv6 ticket-based spin-locking.
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*
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* A memory barrier is required after we get a lock, and before we
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* release it, because V6 CPUs are assumed to have weakly ordered
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* memory.
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*/
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#define arch_spin_unlock_wait(lock) \
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do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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u32 newval;
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arch_spinlock_t lockval;
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__asm__ __volatile__(
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"1: ldrex %0, [%3]\n"
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" add %1, %0, %4\n"
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" strex %2, %1, [%3]\n"
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" teq %2, #0\n"
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" bne 1b"
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: "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
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: "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
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: "cc");
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while (lockval.tickets.next != lockval.tickets.owner) {
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wfe();
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lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
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}
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smp_mb();
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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u32 slock;
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__asm__ __volatile__(
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" ldrex %0, [%2]\n"
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" subs %1, %0, %0, ror #16\n"
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" addeq %0, %0, %3\n"
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" strexeq %1, %0, [%2]"
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: "=&r" (slock), "=&r" (tmp)
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: "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
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: "cc");
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if (tmp == 0) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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u32 slock;
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smp_mb();
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__asm__ __volatile__(
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" mov %1, #1\n"
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"1: ldrex %0, [%2]\n"
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" uadd16 %0, %0, %1\n"
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" strex %1, %0, [%2]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (slock), "=&r" (tmp)
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: "r" (&lock->slock)
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: "cc");
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dsb_sev();
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}
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static inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
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return tickets.owner != tickets.next;
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}
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static inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
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return (tickets.next - tickets.owner) > 1;
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}
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#define arch_spin_is_contended arch_spin_is_contended
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/*
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* RWLOCKS
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*
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*
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* Write locks are easy - we just set bit 31. When unlocking, we can
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* just write zero since the lock is exclusively held.
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*/
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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WFE("ne")
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" strexeq %0, %2, [%1]\n"
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" teq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc");
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smp_mb();
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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" ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc");
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if (tmp == 0) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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smp_mb();
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__asm__ __volatile__(
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"str %1, [%0]\n"
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:
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: "r" (&rw->lock), "r" (0)
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: "cc");
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dsb_sev();
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}
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/* write_can_lock - would write_trylock() succeed? */
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#define arch_write_can_lock(x) ((x)->lock == 0)
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/*
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* Read locks are a bit more hairy:
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* - Exclusively load the lock value.
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* - Increment it.
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* - Store new lock value if positive, and we still own this location.
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* If the value is negative, we've already failed.
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* - If we failed to store the value, we want a negative result.
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* - If we failed, try again.
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* Unlocking is similarly hairy. We may have multiple read locks
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* currently active. However, we know we won't have any write
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* locks.
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" adds %0, %0, #1\n"
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" strexpl %1, %0, [%2]\n"
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WFE("mi")
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" rsbpls %0, %1, #0\n"
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" bmi 1b"
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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smp_mb();
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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smp_mb();
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" sub %0, %0, #1\n"
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" strex %1, %0, [%2]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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if (tmp == 0)
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dsb_sev();
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}
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned long tmp, tmp2 = 1;
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__asm__ __volatile__(
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" ldrex %0, [%2]\n"
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" adds %0, %0, #1\n"
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" strexpl %1, %0, [%2]\n"
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: "=&r" (tmp), "+r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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smp_mb();
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return tmp2 == 0;
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}
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/* read_can_lock - would read_trylock() succeed? */
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#define arch_read_can_lock(x) ((x)->lock < 0x80000000)
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#endif /* __ASM_SPINLOCK_H */
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