be02ff9940
flush_write_buffers() in dma-mapping-common.h was removed so we can remove NULL flush_write_buffers() in IA64. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com Cc: davem@davemloft.net LKML-Reference: <1249872797-1314-3-git-send-email-fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Ingo Molnar <mingo@elte.hu>
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
#ifndef _ASM_IA64_DMA_MAPPING_H
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#define _ASM_IA64_DMA_MAPPING_H
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/*
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* Copyright (C) 2003-2004 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*/
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#include <asm/machvec.h>
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#include <linux/scatterlist.h>
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#include <asm/swiotlb.h>
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#include <linux/dma-debug.h>
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#define ARCH_HAS_DMA_GET_REQUIRED_MASK
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extern struct dma_map_ops *dma_ops;
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extern struct ia64_machine_vector ia64_mv;
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extern void set_iommu_machvec(void);
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extern void machvec_dma_sync_single(struct device *, dma_addr_t, size_t,
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enum dma_data_direction);
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extern void machvec_dma_sync_sg(struct device *, struct scatterlist *, int,
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enum dma_data_direction);
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *daddr, gfp_t gfp)
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{
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struct dma_map_ops *ops = platform_dma_get_ops(dev);
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void *caddr;
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caddr = ops->alloc_coherent(dev, size, daddr, gfp);
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debug_dma_alloc_coherent(dev, size, *daddr, caddr);
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return caddr;
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}
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static inline void dma_free_coherent(struct device *dev, size_t size,
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void *caddr, dma_addr_t daddr)
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{
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struct dma_map_ops *ops = platform_dma_get_ops(dev);
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debug_dma_free_coherent(dev, size, caddr, daddr);
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ops->free_coherent(dev, size, caddr, daddr);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define get_dma_ops(dev) platform_dma_get_ops(dev)
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#include <asm-generic/dma-mapping-common.h>
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static inline int dma_mapping_error(struct device *dev, dma_addr_t daddr)
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{
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struct dma_map_ops *ops = platform_dma_get_ops(dev);
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return ops->mapping_error(dev, daddr);
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}
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static inline int dma_supported(struct device *dev, u64 mask)
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{
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struct dma_map_ops *ops = platform_dma_get_ops(dev);
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return ops->dma_supported(dev, mask);
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}
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static inline int
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dma_set_mask (struct device *dev, u64 mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = mask;
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return 0;
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}
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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if (!dev->dma_mask)
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return 0;
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return addr + size <= *dev->dma_mask;
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}
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static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return paddr;
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}
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static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return daddr;
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}
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extern int dma_get_cache_alignment(void);
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static inline void
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dma_cache_sync (struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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/*
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* IA-64 is cache-coherent, so this is mostly a no-op. However, we do need to
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* ensure that dma_cache_sync() enforces order, hence the mb().
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*/
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mb();
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}
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#define dma_is_consistent(d, h) (1) /* all we do is coherent memory... */
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#endif /* _ASM_IA64_DMA_MAPPING_H */
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